• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.9
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• pp.2023-2030
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• 2010

In this paper, we present research results of developing high performance scan conversion unit and implementing it on FPGA chip. To increase performance of scan conversion unit, we propose an architecture of scan converter that is a SIMD architecture and uses tile-based traversing method. The proposed scan conversion unit can operate about 124Mhz clock frequency on Xilinx Vertex4 LX100 device. To verify the scan conversion unit, we also develop shader unit, texture mapping unit and $240{\times}320$ color TFT-LCD controller to display outputs of the scan conversion unit on TFT-LCD. Because the scan conversion unit implemented on FPGA has 311Mpixels/sec pixel rate, it is applicable to desktop pc's 3d graphics system as well as mobile 3d graphics system needing high pixel rates.

• Journal of Magnetics
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• v.13 no.2
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• pp.37-42
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• 2008

In this paper, design parameters of high Q (> 50), high current inductor for on-chip power module were optimized by 4 Xs 3 Ys DOE (Design of Experiment). Coil spacing, coil thickness, ferrite thickness, and permeability were assigned to Xs, and inductance (L) and Q factor at 10 MHz, and resonance frequency ($f_r$) were determined Ys. Effects of each X on the Ys were demonstrated and explained using known inductor theory. Multiple response optimizations were accomplished by three derived regression equations on the Ys. As a result, L of 125 nH, Q factor of 197.5, and $f_r$ of 316.3 MHz were obtained with coil space of $127\;{\mu}m$, Cu thickness of $67.8\;{\mu}m$, ferrite thickness of $130.3\;{\mu}m$, and permeability 156.5. Loss tan ${\delta}=0$ was assumed for the estimation. Accordingly, Q factor of about 60 is expected at tan ${\delta}=0.02$.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.12
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• pp.155-160
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• 2003

Owing to the advances in ADC and DSP technologies, signals in If band, which once had to be processed in analog technology, can new be digitally processed. This is referred to as "Digital IF" or "Digital Radio", which is a preliminary stage of SDR. Applying the digital radio technology to a multi-carrier receiver design, a processing gain is generated through an over-sampling of input data. In the digital receiver, decimation is performed for reducing the computational complexity CIC and half band filter is used together with the decimation as an anti-alising filter. The CIC filter, however, should introduce the roll-off phenomenon in the passband, which causes the receiving performance to be considerably degraded due to the distorted Passband flatness of receiving filter. In this paper, we designed a CIC roll-off compensation filter for W-CDMA digital receiver. The performance of the proposed compensation filter is confirmed through computer simulations in such a way that the BER is minimized by compensating the roll-off characteristics.off characteristics.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.4
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• pp.393-400
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• 2014

In this paper, we have designed the transmitter for earth station terminal operating with military geostationary satellite on Ka-band that is complied with MIL-STD-188-164A. The designed antenna of this terminal is dual-offset gregorian reflector which is consist of corrugated horn and iris polarizer, othermode transducer. This antenna meets radiation pattern and transmit EIRP spectral density requirements in this standard. The designed RF systems of this terminal are consist of Block Up Converter(BUC) converting frequency band from IF to Ka band and SSPA having low-power consumption and compact light-weight using the pHEMT MMIC compound devices. This RF systems applied with VSWR, spurious/harmonic suppression, output flatness and phase noise requirement in this standard.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.1-8
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• 2009

We designed an ADC that operated upto 500Msamples/sec based on proposed R-string folding block as well as second folding block. The upper four bits are processed in parallel by the R-string folding block while the lower four bits are processed in pipeline structured second folding block to supply digital output. To verify the circuit performance, we conducted HSPICE simulation and the average power consumption was only 1.34mW even when the circuit was running at its maximum sampling frequency. We further measured noise immunity by applying linear ramp signal to the input. The DNL was between -0.56*LSB and 0.49*LSB and the INL was between -0.93*LSB and 0.72*LSB. We used 0.35 microns MOSIS device parameters for this work.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.1
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• pp.78-84
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• 2012

In this paper, we introduced the design technique about a Ka band receive module for millimeter wave seekers. The receiver module consists of a waveguide, circulator and transition for antenna connection, and a limiter and gain control amplifier for receiver protection. This module is comprised of a sum, azimuth and elevation channel for receiving monopules signal, and a SLB channel for the acquisition of jamming signal. In this paper, receiver gain and range of gain control dependent on ADC nonlinear characteristic was analyzed and designed for wide dynamic range receive. In the test result of the fabricated Ka-band receive, the frequency band is 1 GHz, the noise figure is as low as 8.2 dB, the gain is $56{\pm}2dB$, the dynamic range is 135 dB, the gain congtrol is more than 86 dB, the channel isolation is more than 35 dB.

• Journal of Fashion Business
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• v.4 no.4
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• pp.17-28
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• 2000

The purpose of this study is to analyze the recognition of and the preference for a fashion specialist among students from 4-year and 2-year colleges in Taegu, in order to provide basic data for the effective management methods for the students. The objects of the survey were students in Taegu and Kyungbuk province; 287 students from 4-year colleges and 430 students from 2-year colleges, making the total of 717 students. The survey tool was a questionnaire, which consists of 7 general questions, 7 major curriculum related questions, and 6 questions regarding the information about a fashion specialist, and students career plan. It also contains 3-level Licurt type questionnaire on the recognition of and the preference for a fashion specialist from 20 professional fields. SPSS is used for frequency, percentage, average, standard deviation, $x^2$-test and ANOVA. The results of this study are as follows: 1. The students' motivation in choosing their major as clothing and fashion design was out of independent career plan (86.7%). They were quite content with their major but were unsatisfactory with the current curriculum. 2. The subjects students thought necessary in preparing to be a fashion specialist were pattern, clothing construction (40.1%), clothing design (33.7%), and fashion marketing (18.9%). The answer to the question about the most important subject in the future was fashion marketing (57.2%). 3. What students consider most in choosing a job was aptitude and ability (70.8%). The most preferable clothing types that students want to work with after graduation were womens clothing (52.1%) and wedding dress (18.1%). 4. The means of getting information on a fashion specialist were magazines or broadcasting (72%) and school lectures (20.6%), and there was a significant deference among colleges. 5. Fashion coordinator was the highest recognized specialist (2.64) and the lowest was fashion converter (1.23) among other fashion specialists. 4-year college students had higher recognition in all areas (20 areas) than 2-year college students, and there was a significant deference among colleges in 20 areas.

• Journal of Power Electronics
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• v.16 no.3
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• pp.1110-1121
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• 2016

The mathematical model of a three phase PWM converter under the stationary αβ reference frame is deduced and constructed based on a Proportional-Resonant (PR) regulator, which can replace trigonometric function calculation, Park transformation, real-time detection of a Phase Locked Loop and feed-forward decoupling with the proposed accurate calculation of the inductance voltage vector. To avoid the parallel resonance of the LCL topology, the active damping method of the proportional capacitor-current feedback is employed. As to current vector error elimination, an optimized PR controller of the inner current loop is proposed with the zero-pole matching (ZPM) and cancellation method to configure the regulator. The impacts on system's characteristics and stability margin caused by the PR controller and control parameter variations in the inner-current loop are analyzed, and the correlations among active damping feedback coefficient, sampling and transport delay, and system robustness have been established. An equivalent model of the inner current loop is studied via the pole-zero locus along with the pole placement method and frequency response characteristics. Then, the parameter values of the control system are chosen according to their decisive roles and performance indicators. Finally, simulation and experimental results obtained while adopting the proposed method illustrated its feasibility and effectiveness, and the inner current loop achieved zero static error tracking with a good dynamic response and steady-state performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.1-6
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• 2007

Wireless Self-Powered Temperature Sensor for UHF Sensor Tags which are basic device for construction of ubiquitous sensor network is proposed. The key parameters of the target specification are resolution of $0.1\;^{\circ}C$ per output bit, below 1.5 V of operating voltage and below 5 uW of power consumption during sensing operation. Temperature sensor circuit consists of PTAT current generator, band gap reference circuit generating both reference voltage and current, Sigma-Delta Converter, and Digital Counter. Simulated maximum resolution was $0.23\;^{\circ}C/bit$ in 11-bit output. The proposed temperature sensor was fabricated by using a 0.25 m CMOS process. The chip area is $0.32\;{\times}\;0.22\;mm$ and the operating frequency is 2 MHz. Measured resolution from fabricated temperature sensor was $4\;^{\circ}C/bit$ in 8-bit output for the temperature range from $10^{\circ}C$ to $80^{\circ}C$.

• Journal of Power Electronics
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• v.16 no.1
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• pp.227-237
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• 2016

A novel digital current control strategy for digitally controlled DC-DC switching converters, referred to as Adjacent Cycle Sampling (ACS), is proposed in this paper. For the ACS current control strategy, the available time interval from sampling the current to updating the duty ratio, is approximately one switching cycle. In addition, it is independent of the duty ratio. As a result, the contradiction between the processing speed of the hardware and the transient response speed can be effectively relaxed by using the ACS current control strategy. For digitally controlled buck DC-DC switching converters with trailing-edge modulation, digital current control algorithms with the ACS control strategy are derived for three different control objectives. These objectives are the valley, average, and peak inductor currents. In addition, the sub-harmonic oscillations of the above current control algorithms are analyzed and eliminated by using the digital slope compensation (DSC) method. Experimental results based on a FPGA are given, which verify the theoretical analysis results very well. It can be concluded that the ACS control has a faster transient response speed than the time delay control, and that its requirements for hardware processing speed can be reduced when compared with the deadbeat control. Therefore, it promises to be one of the key technologies for high-frequency DC-DC switching converters.