• Title/Summary/Keyword: Frequecy Synthesizer

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Design of PLL Frequency Synthesizer for a 915MHz ISM Band wireless transponder using CPFSK communication (CPFSK communication 사용한 915MHz ISM Band 위한 PLL Frequency Synthesizer 설계)

  • Kim, Seung-Hoon;Cho, Sang-Bock
    • Proceedings of the KIEE Conference
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    • 2007.04a
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    • pp.286-288
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    • 2007
  • In this paper, the fast locking PLL Frequency Synthesizer with low phase noise in a 0.18um CMOS process is presented. Its main application IS for the 915MHz ISM band wireless transponder upon the CPFSK (Continuous Phase Frequency Shift Keying) modulation scheme. Frequency synthesizer, which in this paper, is designed based on self-biased techniques and is independent with processing technology when damping factor and bandwidth fixed to most important parameters as operating frequency ratio, broad frequency range, and input phase offset cancellation. The proposed frequecy synthesizer, which is fully-integrated and is in 320M $^{\sim}$ 960MHz of the frequency range with 10MHz of frequency resolution. And its is implemented based on integer-N architecture. Its power consumption is 50mW at 1.8V of supply voltage and core area is $540{\mu}m$ ${\times}$ $450{\mu}m$. The measured phase noises are -117.92dBc/Hz at 10MHz offset, with low settling time less than $3.3{\mu}s$.

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Design of a 48MHz~1675MHz Frequency Synthesizer for DTV Tuners (DTV 튜너를 위한 48MHz~1675MHz 주파수합성기 설계)

  • Ko, Seung-O;Seo, Hee-Teak;Kwon, Duck-Ki;Yu, Chong-Gun
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.5
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    • pp.1125-1134
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    • 2011
  • In this paper a wideband frequency synthesizer is designed for DTV tuners using a $0.18{\mu}m$ CMOS process. It satisfies the DTV frequency band(48~1675MHz). A scheme is proposed to cover the full band using only one VCO and reliable broadband characteristics are achieved by reducing the variations of VCO gains and frequency steps. The simulation results show that the designed VCO has frequency range of 1.85~4.22GHz, phase noise at 4.22GHz of -89.7dBc/Hz@100kHz, gains of 62.4~95.8MHz/V(${\pm}21.0%$) and frequency steps of 22.9~47.9MHz(${\pm}35.3%$). The designed VCO has a phase noise of -89.75dBc/Hz at 100kHz offset. The designed synthesizer has a lock time less than $0.15{\mu}s$. The measured VCO tuning range is 2.05~3.4GHz. The frequency range is shifted down but still satisfy the target range owing to the design for enough margin. The designed circuit consumes 23~27mA from a 1.8V supply, and the chip size including PADs is $2.0mm{\times}1.5mm$.