• 한국HCI학회:학술대회논문집
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• 2008.02a
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• pp.534-539
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• 2008

This paper is about intelligent hexapod robot for the support walking of the aged person. The robot using various sensors and small camera has various abilities of forward backward walking, turing left or right, control the speed of walking, avoiding the obstacles and detecting risky situation of fire or gas. To let the aged feel soft and safe walking, we used special servo motor and developed hexapod walking mechanism and effective algorithm.

• Journal of Information Technology Services
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• v.19 no.1
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• pp.145-158
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• 2020

With the development and widespread application of online shopping, the number of online consumers has increased. With one click of a mouse, people can buy anything they want without going out and have it sent right to the doors. As consumers benefit from online shopping, people are becoming more concerned about protecting their privacy. In the group buying scenario described in our paper, online shopping was regarded as intra-group communication. To protect the sensitive information of consumers, the polynomial-based encryption key sharing method (Piao et al., 2013; Piao and Kim, 2018) can be applied to online shopping communication. In this paper, we analyze security problems by using a polynomial-based scheme in the following ways : First, in Kamal's attack, they said it does not provide perfect forward and backward secrecy when the members leave or join the group because the secret key can be broken in polynomial time. Second, for simultaneous equations, the leaving node will compute the new secret key if it can be confirmed that the updated new polynomial is recomputed. Third, using Newton's method, attackers can successively find better approximations to the roots of a function. Fourth, the Berlekamp Algorithm can factor polynomials over finite fields and solve the root of the polynomial. Fifth, for a brute-force attack, if the key size is small, brute force can be used to find the root of the polynomial, we need to make a key with appropriately large size to prevent brute force attacks. According to these analyses, we finally recommend the use of a relatively reasonable hash-based mechanism that solves all of the possible security problems and is the most suitable mechanism for our application. The study of adequate and suitable protective methods of consumer security will have academic significance and provide the practical implications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.9
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• pp.745-752
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• 1990

This paper deals with the path sensitization algrithm from PI to PO center on the nodes of high testability mainstay when CUT is tested by pseudo exhaustive testing. In CUT, the node definition of high testability mainstay treats the testability values of the entire nodes with the population composed of the raw data, and after we examined the level of significance(1-a) region, we accomplished in the estimation of the confidence interval of the testability. Focusing on the defined nodes of high testability mainstay, we performed the singular cover and consistency operation to the forward and backward logic gates. Thus, we easily generated the pseudo exhausitve test patterns. As a result, (1-a) region has 0.1579 and the pseudo exhaustive test patterns are least generated and the rate of test pattern is 1.22%, compared with exhaustive testing. (1-a) region has 0.2368 and this results exhibits the optimal performance of the singular cover and consistency operation. Applying the generated pseudo exhaustive test patterns to the stuck-at faults existing on the inputs and internal nodes in CUT, we verified this performance on the output. Thus, it is confirmed that functional testing of the proposed path sensitization algorithm is very useful.

• The Korean Journal of Physiology and Pharmacology
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• v.21 no.5
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• pp.555-563
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• 2017

Electrical stimulation through retinal prosthesis elicits both short and long-latency retinal ganglion cell (RGC) spikes. Because the short-latency RGC spike is usually obscured by electrical stimulus artifact, it is very important to isolate spike from stimulus artifact. Previously, we showed that topographic prominence (TP) discriminator based algorithm is valid and useful for artifact subtraction. In this study, we compared the performance of forward backward (FB) filter only vs. TP-adopted FB filter for artifact subtraction. From the extracted retinae of rd1 mice, we recorded RGC spikes with $8{\times}8$ multielectrode array (MEA). The recorded signals were classified into four groups by distances between the stimulation and recording electrodes on MEA (200-400, 400-600, 600-800, $800-1000{\mu}m$). Fifty cathodic phase-$1^{st}$ biphasic current pulses (duration $500{\mu}s$, intensity 5, 10, 20, 30, 40, 50, $60{\mu}A$) were applied at every 1 sec. We compared false positive error and false negative error in FB filter and TP-adopted FB filter. By implementing TP-adopted FB filter, short-latency spike can be detected better regarding sensitivity and specificity for detecting spikes regardless of the strength of stimulus and the distance between stimulus and recording electrodes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.3
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• pp.21-29
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• 2012

This paper presents optimized searching technique to improve the performance of H.264/AVC. By using the proposed forward and backward searching algorithm, redundant cycles of latency for data reordering can be removed. Furthermore, in order to reduce the total number of execution cycles of CAVLC encoder, early termination mode and two stage pipelined architecture are proposed. The experimental result shows that the proposed architecture needs only 36.0 cycles on average for each $16{\times}16$ macroblock encoding. The proposed architecture improves the performance by 57.8% than that of previous designs. The proposed CAVLC encoder was implemented using Verilog HDL and synthesized with Magnachip $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count is about 17K with 125Mhz clock frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.12
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• pp.1834-1843
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• 2016

DVRs are the most common recording and displaying devices used for surveillance. Video compression plays a key role in DVRs for saving storage; the video compression standard, H.264/AVC, has recently become the dominant choice for DVRs. DVRs require various display modes, such as fast-forward, backward play, and pause; these are called trick modes. The implementation of precise trick mode play requires a very high decoding capability or a very intelligent scheme in order to handle the high computation complexity. The complexity is increased in many surveillance applications where more than one camera is used to monitor multiple spots or to monitor the same area using various angles. An implementation of a trick mode play and a frame buffer management scheme for the hardware-based H.264/AVC codec for multi-channel is presented in this paper. The experimental results show that exact trick mode play is possible using a standard H.264/AVC video codec with keyframe encoding feature at the expense of bitstream size increase.

• The Journal of the Korea Contents Association
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• v.15 no.5
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• pp.18-26
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• 2015

In this paper, we presented a design and control method of multi-stage with wagon and lift stage. Multi-stage system has 4 degree-of-freedom(DOF), i.e., forward/backward/left/right/rotate and up/down motion. Wagon mechanism in the type of two wheel and steering is proposed in order to improve for the maneuverability compared to the existing differential-type wagons. Also, the lift mechanism is designed by interlocking type in order to make the maximum height bigger than 10 times of the original height. We also proposed a path planning algorithm. The performance of the propped system is validated via multi motion experiments, so that the multi-stage system is useful for various performances production.

• Journal of Biosystems Engineering
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• v.43 no.4
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• pp.273-284
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• 2018

Purpose: Conventional headland turning typically requires repeated forward and backward movements to move the farming equipment to the next row. This research focuses on developing an upland agricultural robot with an optimized headland turning mechanism that enables a $180^{\circ}$ turning positioning to the next row in one steering motion designed for a two-wheel steering, four-wheel drive agricultural robot named the HADA-bot. The proposed steering mechanism allows for faster turnings at each headland compared to those of the conventional steering system. Methods: The HADA-bot was designed with 1.7-m wide wheel tracks to travel along the furrows of a garlic bed, and a look-ahead path following algorithm was applied using a real-time kinematic global positioning system signal. Pivot turning tests focused primarily on accuracy regarding the turning radius for the next path matching, saving headland turning time, area, and effort. Results: Several test cases were performed by evaluating right and left turns on two different surfaces: concrete and soil, at three speeds: 1, 2, and 3 km/h. From the left and right side pivot turning results, the percentage of lateral deviation is within the acceptable range of 10% even on the soil surface. This U-turn scheme reduces 67% and 54% of the headland turning time, and 36% and 32% of the required headland area compared to a 50 hp tractor (ISEKI, TA5240, Ehime, Japan) and a riding-type cultivator (CFM-1200, Asia Technology, Deagu, Rep. Korea), respectively. Conclusion: The pivot turning trajectory on both soil and concrete surfaces achieved similar results within the typical operating speed range. Overall, these results prove that the pivot turning mechanism is suitable for improving conventional headland turning by reducing both turning radius and turning time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.185-197
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• 2001

Recently, the design method by VHDL coding and synthesis has been used widely. As the integration ratio increases, the amount design by VHDL at a time also increases so many coding errors occur in a design. Thus, lots of time and effort is dissipated to detect those coding errors. This paper proposed a method to verify the coding errors in VHDL behavioral-level designs. As the methodology, we chose the method to detect the coding error by applying the generated set of verifying patterns and comparing the responses from the error-free case(gold unit) and the real design. Thus, we proposed an algorithm to generate the verifying pattern set for the coding errors. Verifying pattern generation is peformed for each code and the coding errors are classified as two kind: condition errors and assignment errors. To generate the patterns, VHDL design is first converted into the corresponding CDFG(Control & Data Flow Graph) and the necessary information is extracted by searching the paths in CDFG. Path searching method consists of forward searching and backward searching from the site where it is assumed that coding error occurred. The proposed algorithm was implemented with C-language. We have applied the proposed algorithm to several example VHDL behavioral-level designs. From the results, all the patterns for all the considered coding errors in each design could be generated and all the coding errors were detectable. For the time to generate the verifying patterns, all the considered designed took less than 1 ［sec］ of CPU time in Pentium-II 400MHz environments. Consequently, the verification method proposed in this paper is expected to reduce the time and effort to verify the VHDL behavioral-level designs very much.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.35 no.2
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• pp.57-63
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• 2012

Software release planning model of software product lines was formulated as a precedence-constrained multiple 0-1 knapsack problem. The purpose of the model was to maximize the total profit of an entire set of selected features in a software product line over a multi-release planning horizon. The solution approach is a dynamic programming procedure. Feasible solutions at each stage in dynamic programming are determined by using backward dynamic programming approach while dynamic programming for multi-release planning is forward approach. The pre-processing procedure with a heuristic and reduction algorithm was applied to the single-release problems corresponding to each stage in multi-release dynamic programming in order to reduce the problem size. The heuristic algorithm is used to find a lower bound to the problem. The reduction method makes use of the lower bound to fix a number of variables at either 0 or 1. Then the reduced problem can be solved easily by the dynamic programming approaches. These procedures keep on going until release t = T. A numerical example was developed to show how well the solution procedures in this research works on it. Future work in this area could include the development of a heuristic to obtain lower bounds closer to the optimal solution to the model in this article, as well as computational test of the heuristic algorithm and the exact solution approach developed in this paper. Also, more constraints reflecting the characteristics of software product lines may be added to the model. For instance, other resources such as multiple teams, each developing one product or a platform in a software product line could be added to the model.