• Proceedings of the KSR Conference
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• 2007.05a
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• pp.1000-1007
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• 2007

Recently, many critical control systems are developed using formal methods. When software applied to such systems is developed, the employment of formal methods in the software requirements specification and verification will provide increased assurance for such applications. Earlier error of overlooked requirement specification can be detected using formal specification method. Also the testing and full verification to examine all reachable states using model checking to undertake formal verification are able to be completed. In the comparison of other formal specification methods, we choose the Z formal language for applying to the train control system. Using Z is able to realize higher correctness in the requirement specification, and we propose the Statemate of the best solution in formal verification tools for the system modeling and verification. The Statemate makes it possible to prove thoroughly the system execution from the simple graphical modeling of the complicated train control system. Then we can expect that the model-based formal method combining Z with Statemate will be utilized widely for the railway systems due to various strong points.

• Journal of KIISE:Computing Practices and Letters
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• v.12 no.2
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• pp.141-148
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• 2006

This paper suggests method of safe security S/W by verifying and its result of formal verification tool. We will survey many formal verification tools and compare features of these tools. And we will suggest what tool is appropriate and methodogoly of developing safe security S/W. The Z/EVES is the most appropriate tool. This paper proposes formal verification of ACS by using RoZ tool which is formal verification tool to create UML model. The specification and verification are executed using Z/EVES tool. These procedures can find weak or wrong point of developed S/W.

• Journal of Electrical Engineering and Technology
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• v.4 no.1
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• pp.87-92
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• 2009

Many critical control systems are developed using formal methods. When software applied to such systems is developed, the employment of formal methods in the software requirements specification and verification will provide increased assurance for such applications. Earlier errors of overlooked requirement specification can be detected using the formal specification method. Also, the testing and full verification to examine all reachable states using model checking to undertake formal verification are able to be completed. In this paper, we proposed an eclectic approach to incorporate Z(Zed) formal language and 'Statemate MAGNUM', formal method tools using Statechart. Also we applied the proposed method to train control systems for the formal requirement specification and analyzed the specification results.

• Journal of the Korea Safety Management & Science
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• v.17 no.1
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• pp.179-192
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• 2015

In an automated industry PLC plays a central role to control the automation system. Therefore, fault free operation of PLC controlled automation system is essential in order to maximize a firm's productivity. A prior test of control system is a practical way to check fault operations, but it is a time consuming job and can not check all possible fault operation. A formal verification of PLC program could be a best way to check all possible fault situation. Tracing the history of the study on formal verification, we found three problems, the first is that a formal representation of PLC control system is incomplete, the second is a state explosion problem and the third is that the verification result is difficult to use for the correction of control program. In this paper, we propose a transformation method to reproduce the control system correctly in formal model and efficient procedure to verify and correct the control program using verification result. To demonstrate the proposed method, we provided a suitable case study of an automation system.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.1
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• pp.46-61
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• 2002

Among the many phases involved in software development, requirements analysis phase in generally considered to play a crucial role in determining the overall software quality. Therefore, many software development companies manages the phase as one of the important phase. Especially, safety assurance through requirements analysis for safety-critical systems is quite demanding, and national and international bodies routinely require safety demonstration. Among various approaches, inspection and formal methods are generally shown to be effective. In this paper, we propose a formal verification procedure for SCR(Software Cost Reduction)-style SRS(Software Requirements Specification) using the PVS specification and verification procedure and applied this procedure to an industrial system such that a shutdown system for Wolsung nuclear power plant. This system had been verified through inspection not formal verification. The application of formal methods is rare in Korea, so it is very important to experiment about formal verification to industrial systems.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.939-942
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• 2003

Design verification problem is emerging as an important issue to detect any design errors at the early stage of the design. Conventionally, design verifications have been done using a simulation technique. However, this technique has been proved not to cover all potential design errors. Therefore, formal technique is often used to verify digital circuits as an alternative. In this paper we adopted formal verification technique and verified some important properties derived from our pipelined digital systems, using SMV (Symbolic Model Verifier). Our example shows that model checking method (one of formal verification techniques) can be effectively performed in verifying the large digital systems.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.2
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• pp.65-71
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• 2008

Recently, many critical control systems are developed using formal methods. When software applied to such systems is developed, the employment of formal methods in the software requirements specification and verification will provide increased. assurance for such applications. Earlier error of overlooked requirement specification can be detected using formal specification method. Also the testing and full verification to examine all reachable states using model checking to undertake formal verification are able to be completed. In this paper, we propose an eclectic approach to incorporate Z(Zed) formal language and 'Statemate MAGNUM' which is formal method tools using Statechart for applying to the railway signaling systems.

• Journal of the Korea Society of Computer and Information
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• v.12 no.6
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• pp.123-130
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• 2007

In this paper, We define convert rules from objects and relation presented in object model to the state and operation domain in formal specification. Namely, object and relation in information model converted to state domain in formal specification. State, event and behavior converted to operation domain. And that way informal object model change to formal language, it can be verify through formal method. Verification process make an offer convenience and confidence in software development early phase. And we implement simulation tool in order to verification method of formal specification and to consistency verified model between user's requirement. It is possible to select the suitable model and reduce the costs and efforts on software development.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.358-362
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• 2004

Verification and testing are complementary techniques that are used to increase the level of confidence in the correct functioning of communication systems as prescribed by their specifications. This paper presents an experience of model checking for a formal railway signaling protocol specified in LTS (Labeled Transition System). This formal approach checks deadlock, livelock and reachability for the state and action to verify whether properties expressed in modal logic are true on specifications. We also propose a formal method for semi-automated test case generation for a railway signaling protocol described in I/O FSM (Input/Output Finite State Machine). This enables the generation of more complete and consistent test sequence for conformance testing. The above functions are implemented by C++ language and included within RSPVTE (Railway Signaling Protocol Verification and Testing Environment).

• Journal of the Korean Society for Railway
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• v.7 no.2
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• pp.114-119
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• 2004

According to the computerization of railway signalling systems. the communication protocol for interface between these systems are required. Therefore the new communication protocol for railway signaling system is required. Generally, there are two verification method for new designed protocol in the industrial and academic fields. One is the laboratory testing method which is very popular and general technique. In our research the comparison between existing and new designed protocol for signaling is described and the verification test results are also represented. From these laboratory test, we are verified the conformance of new designed protocol. Another method is verified by formal method. The format verification method is widely used at safety-critical system design but this approach is nor popular at verification communication protocol. However it is very important to verify the safety of new designed protocol for railway signaling system because signaling systems are very safety-critical systems. So, the methodology for formal verification of designed protocol is also reviews in this paper.