• Korean Journal of Fisheries and Aquatic Sciences
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• v.43 no.2
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• pp.159-168
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• 2010

This paper presents a mathematical model and simulation method for investigating the performance of set net systems and fish cage systems influenced by currents and waves. Both systems consist of netting, mooring ropes, a floating collar and sinkers. The netting and ropes were considered flexible structures and the floating collar was considered an elastic structure. Both were modeled on a mass-spring model. The structures were divided into finite elements and mass points were placed at the mid-point of each element, and the mass points were connected by mass-less springs. Each mass point was subjected to external and internal forces and the total force was calculated at every integration step. An implicit integration scheme was used to solve the nonlinear dynamic system. The computation method was applied to dynamic simulation of actual systems simultaneously influenced by currents and waves in order to evaluate their practicality. The simulation results improved our understanding of the behavior of the structure and provided valuable information concerning the optimized design of set net and fish cage systems exposed to an open ocean environment.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1891-1898
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• 2013

To efficiently execute 3D graphic APIs, such as OpenGL and Direct3D, special purpose arithmetic unit(SFU) which supports floating-point sine, cosine, reciprocal, inverse square root, base-two exponential, and logarithmic operations is designed. The SFU uses second order minimax approximation method and lookup table method to satisfy both error less than 2 ulp(unit in the last place) and high speed operation. The designed circuit has about 2.3-ns delay time under 65nm CMOS standard cell library and consists of about 23,300 gates. Due to its maximum performance of 400 MFLOPS and high accuracy, it can be efficiently applicable to mobile 3D graphics application.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.2
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• pp.139-144
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• 2011

The modern digital logic technology does not yet satisfy the speed requirements of real-time DSP circuits due to synchronized operation of multiplication and accumulation. This operation degrades DSP performance. Therefore, the double-base number system (DBNS) has emerged in DSP system as an alternative methodology because of fast multiplication and hardware simplicity. In this paper, authors propose a novel multiplication architecture. One operand is an output of a flash analog-to-digital converter (ADC) in DBNS format, while the other operand is a coefficient in the IEEE standard floating-point number format. The DBNS digital output from ADC is produced through a new double base number encoder (DBNE). The multiplied output is in the format of the IEEE standard floating-point number (FPNS). The proposed circuits process multiplication and conversion together. Compared to a typical multiplier that uses the FPNS, the proposed multiplier also consumes 45% less gates, and 44% faster than the FPNS multiplier on Spartan-3 FPGA board. The design is verified with FIR filter applications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.547-554
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• 2008

In this paper, two-stage pipelined floating-point multiplier (FP-MUL) is designed. The FP-MUL processor supports single precision multiplication for 3D graphic APIs, such as OpenGL and Direct3D and has area-efficient and low-latency architecture via saturated arithmetic, area-efficient sticky-bit generator, and flagged prefix adder. The FP-MUL has about 4-ns delay time under $0.13{\mu}m$ CMOS standard cell library and consists of about 7,500 gates. Because its maximum performance is about 250 MFLOPS, it can be applicable to mobile 3D graphics application.

• Journal of Biomedical Engineering Research
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• v.17 no.1
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• pp.49-60
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• 1996

An experimental investigation was performed under steady flow condition to assess hydrodynamic performance of floating-type monoleaflet polymer valves (MLPV) withdifferent leaflet thickness. The St. Jude Medical valve (SJMV) was also used for comparison test. Pressure drops of MLPVS are larger than those for other types of polymer valves and mechanical valves. Furthermore, the thicker is the leaflet thickness of the polymer valve, the larger are the corresponding pressure drop. The velocity profiles for MLPs reveal a large reversed flow region downward to the valve position. The maximum wall shear stresses of MLPVS at a flow rate of $30{\ell}$/min are in the range 50-130 dyn/$cm^2$, and the corresponding maximum Reynolds shear stresses are in the range of 100-500 dyn/$cm^2$, respectively, which are beyond the allowable limit clinically. In contrast, floating-type monoleaflet polymer valves show better hydrodynamic performance in leakage volume. From the designing point of view, it may be concluded that the optimum thickness of leaflet for better hydrodynamic performance is one of the Important parameters.

• Proceedings of the KOSOMBE Conference
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• v.1995 no.05
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• pp.241-246
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• 1995

An experimental investigation was performed under steady flow condition to assess hydrodynamic performance of floating-type monoleaflet polymer valves (MLPV) with different leaflet thickness. The St. Jude Medical valve (SJMV) was also used for comparison tests. Pressure drops of MLPVs are larger than those for other types of polymer valves and mechanical valves. Furthermore, the thicker is the leaflet thickness of a polymer valve, the larger arc the corresponding press drop. The velocity profiles for MLPV reveal a large reversed flow region downward to the valve position. The maximum wall shear stresses of MLPVs at a flow rate of 30 l/min are in the range $54-130\;dyn/cm^2$, and the corresponding maximum. Reynolds shear stresses are in the range of $100-500\;dyn/cm^2$, respectively. Both arc beyond the allowable limit clinically. In contrast, floating-type monoleaflet polymer valves show better hydrodynamic performance in leakage volume. From the designing point of view, it can be concluded that the optimum thickness of leaflet for better hydrodynamic performance is one of the important parameters.

• Journal of the Society of Naval Architects of Korea
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• v.46 no.6
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• pp.659-666
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• 2009

Recently, there are several problems in space, contiguity and facility of the existing harbors issued due to the trend of enlarging the container capacity of the large container vessel, the Mobile Harbor has been proposed conceptually as an effective solution for those problems. This concept is a kind of transfer loader of the containers from the large container ship, which is a floating barge with a catamaran type in the underwater part, and so prompt maneuverability and work effectiveness. For the safe mooring of two floating bodies, a container and the mobile harbor, in the near sea apart from the quay, a robot arm mooring facility specially devised would be designed and verified through comparison study under various environmental sea condition in the inner and outer harbor. DP system (Dynamic Positioning System) using the azimuth thruster and a pneumatic fender, etc, will be considered as a next research topic for the mooring security of multi-body floaters.

• Geomechanics and Engineering
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• v.30 no.3
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• pp.273-280
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• 2022

A certain amount of random vibration excitation to subway track is caused by subway operation. This excitation is transmitted through track foundation, tunnel, soil medium, and ground building to the ground and ground structure, causing vibration. The vibration affects ground building. In this study, the results of ANSYS numerical simulation was used to establish back-propagation (BP) neural network model. Moreover, a back-propagation neural network model consisting of five input neurons, one hidden layer, 11 hidden-layer neurons, and three output neurons was used to analyze and calculate the vertical Z-vibration level of New Capital's ground buildings of Qingdao Metro phase I Project (Line M3). The Z-vibration level under different working conditions was calculated from monolithic roadbed, steel-spring floating slab roadbed, and rubber-pad floating slab roadbed under the working condition of center point of 0-100 m. The steel-spring floating slab roadbed was used in the New Capital area to monitor the subway operation vibration in this area. Comparing the monitoring and prediction results, it was found that the prediction results have a good linear relationship with lower error. The research results have good reference and guiding significance for predicting vibration caused by subway operation.

• Journal of Wind Energy
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• v.14 no.1
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• pp.29-36
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• 2023

The analysis of the floating offshore wind turbine platform is based on the procedures provided by the IEC including the International Classification Society, which recommends the analysis in the time domain. But time-domain simulation requires a lot of time and resources to solve tens of thousands of DLCs. This acts as a barrier in terms of floating structure development. For final verification, it requires very precise analysis in the time domain, but from an initial design point of view, a simplified verification procedure to predict the quantity of materials quickly and achieve relatively accurate results is crucial. In this study, a structural design procedure using a design wave applied in the oil and gas industries is presented combined with a conservative turbine load. With this method, a quick design spiral can be rotated, and it is possible to review FOWTs of various shapes and sizes. Consequently, a KRISO Semi-Submersible FOWT platform was developed using a simplified design procedure in frequency-domain analysis.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.113-116
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• 2002

This paper describes a design of 8192-Point pipelined FFT/IFFT processor (PFFTSk) core for DVB-T and DMT-based VBSL modems. A novel two-step convergent block floating -point (75_CBFP) scaling method is proposed to improve the signal- to-quantization-noise ratio (SeNR) of FFT/IFFT results. Our approach reduces about 80% of memory when compared with conventional CBFP methods. The PFFTSk core, which is designed in VHDL and synthesized using 0.25-${\mu}{\textrm}{m}$ CMOS library, has about 76,300 gates, 390k bits RAM, and Twiddle factor ROM of 39k bits. Simulation results show that it can safely operate up to 50-MHz clock frequency at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-$mutextrm{s}$. The SQNR of about 60-dB is achieved.