• Title/Summary/Keyword: Floating Point Calculation

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A Design of 24-bit Floating Point MAC Unit for Transformation of 3D Graphics (3차원 그래픽의 트랜스포메이션을 위한 24-bit 부동 소수점 MAC 연산기의 설계)

  • Lee, Jungwoo;Kim, Woojin;Kim, Kichul
    • IEMEK Journal of Embedded Systems and Applications
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    • v.4 no.1
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    • pp.1-8
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    • 2009
  • This paper proposes a 24-bit floating point multiply and accumulate(MAC) unit that can be used in geometry transformation process in 3D graphics. The MAC unit is composed of floating point multiplier and floating point accumulator. When separate multiplier and accumulator are used, matrix calculation, used in the transformation process, can't use continuous accumulation values. In the proposed MAC unit the accumulator can get continuous input from the multiplier and the calculation time is reduced. The MAC unit uses about 4,300 gates and can be operated at 150 MHz frequency.

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A study about rotor position estimation enhance using IQ math in DSP (DSP 내의 IQ math를 이용한 회전자 위치 추정 정밀도 향상에 관한 연구)

  • Jang, Joong-Hack;Lee, Kwang-Ho;Hong, Sun-Ki
    • Proceedings of the KIEE Conference
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    • 2005.10c
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    • pp.98-100
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    • 2005
  • DSPs used at motor control are usually fixed point processor. They need scaling because they cannot excute floating point calculation. Scaling for floating point calculation makes the DSP's speed down, complex coding and etc. Therefore the IQ math is adopted. IQ math makes the fixed point processor possible to calculate the floating point math. In addition, IQ math can reduce memory usage and be more faster than that without IQ math. It seems that IQ math is appropriate in motor position control. In comparison of the position calculation between the IQ math, math function and the sine table, the method using IQ math is superior than other methods.

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Development of an Intellectual Property Core for Floating Point Calculation for Safety Critical MMIS

  • Mwilongo, Nelson Josephat;Jung, Jae Cheon
    • Journal of the Korean Society of Systems Engineering
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    • v.17 no.2
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    • pp.37-48
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    • 2021
  • Improving the plant protection system against unforeseen changes/transients during operation is essential to maintain plant safety. Under this condition, it requires rapid and accurate signal processing. The use of an Intellectual Property (IP) core for floating point calculations for Safety Critical MMIS can make numerical computations easier and more precise, improving system accuracy. It can represent and manipulate rational numbers as well as a much broader range of values with dynamic range in nuclear power plant. Systems engineering approach (SE) is used through the development process, it helps to reduce complexity and avoid omissions and invalid assumptions as delivers a better understanding of the stakeholders needs. For the implementation on the FPGA target board, the 32-bit floating-point arithmetic with IEEE-754 standards has designed using Simulink model in Matlab for all operations of addition, subtraction, multiplication and division and VHDL code generated.

A Efficient Calculation for log and exponent with A Dual Phase Instruction Architecture (효율적인 로그와 지수 연산을 위한 듀얼 페이즈 명령어 구조)

  • Kim, Jun-Seo;Lee, Kwang-Yeob;Kwak, Jae-Chang
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2010.05a
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    • pp.320-323
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    • 2010
  • This paper proposes efficient log and exponent calculation methods using a dual phase instruction set without additional ALU unit for a mobile enviroment. Using the Dual Phase Instruction set, it extracts exponent and mantissa from expression of floating point and calculates 24bit single precision floating point of log approximation using the Taylor series expansion algorithm. And with dual phase instruction set, it reduces instruction excution cycles. The proposed Dual Phase architecture reduces the performance degradation and maintain smaller size.

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A Design of Dual-Phase Instructions for a effective Logarithm and Exponent Arithmetic (효율적인 로그와 지수 연산을 위한 듀얼 페이즈 명령어 설계)

  • Kim, Chi-Yong;Lee, Kwang-Yeob
    • Journal of IKEEE
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    • v.14 no.2
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    • pp.64-68
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    • 2010
  • This paper proposes efficient log and exponent calculation methods using a dual phase instruction set without additional ALU unit for a mobile enviroment. Using the Dual Phase Instruction set, it extracts exponent and mantissa from expression of floating point and calculates 24bit single precision floating point of log approximation using the Taylor series expansion algorithm. And with dual phase instruction set, it reduces instruction excution cycles. The proposed Dual Phase architecture reduces the performance degradation and maintain smaller size.

Analysis of Robust Control Algorithms for DVDR Servo using Fixed-Point Arithmetic (고정 소수점 연산을 이용한 DVDR 서보의 강인 제어 알고리즘 해석)

  • 박창범;김홍록;서일홍
    • 제어로봇시스템학회:학술대회논문집
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    • 2000.10a
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    • pp.259-259
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    • 2000
  • In the recent, the size of hardware is smaller and the structure is simpler, without reducing the performance of the digital controller. Accordingly, the fixed-point arithmetic is very important in the digital controller. This paper presents simulation to apply the robust control algorithms to DVDR servo controller using the floating-point and fixed-point arithmetic from the matlab. Also, it analyses and compares the performance of control algorithms in the each of point calculation and presents a method for improvement of drop in the performance, quantization error and overflow/underflow from using the fixed-point arithmetic

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An Approximate Euclidean Distance Calculation for Fast VQ Encoding

  • Baek, Seong-Joon;Kim, Jin-Young;Kang, Sang-Ki
    • Speech Sciences
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    • v.11 no.2
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    • pp.211-216
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    • 2004
  • In this paper, we present a fast encoding algorithm for vector quantization with an approximate Euclidean distance calculation. An approximation is performed by converting floating point to the near integer. An inequality between the approximate Euclidean distance and the nearest distance is developed to avoid unnecessary distance calculations. Since the proposed algorithm rejects those codewords that are impossible to be the nearest codeword, it produces the same output as conventional full search algorithm.

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IEEE Standard Floating Poing ALU with 60MHz Clock Frequency (60MHz Clock 주파수의 IEEE 표준 Floating Point ALU)

  • Yong Surk Lee
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.28A no.11
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    • pp.915-922
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    • 1991
  • This research paper presents an ALU unit using 1.0$\mu$m CMOS technology capable of doing IEEE standard single and double precision floating poing calculation within 32ns (2 clock) at 60 MHz clock speed. This 32ns speed was achieved by using 9ns 1's complement arithmetic 54 bit carry select adder instead of previous 2's complement adders. On the first cycle, this adder is used for addition or subtraction and the second cycle uses this adder for rounding. This reduces the number of required adders from two to one. Speed improvement is 2 to 5 times compared with previous 40MHz design. Design goal was 60MHz, however, this unit is functioning at 80 MHz at room temperature.

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Estimation of Movement Amount of River Floating Debris Based on Effective Rainfall and Flow Rate (유효강우량과 유량에 따른 하천 부유쓰레기 이동량 산출)

  • Jang, Seon-Woong;Yoon, Hong-Joo
    • The Journal of the Korea institute of electronic communication sciences
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    • v.12 no.1
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    • pp.237-242
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    • 2017
  • Along with effluence of non-point pollution source, continuous precipitation due to rainy season or localized heavy rain can also be a good reason for increase of flow rate. And if the water level is going up due to the increase, floating debris around rivers and streams will move because of increased flow velocity. However, currently, there are no studies which perform quantitative calculation on movement of floating debris by analyzing amount of rainfall and flow rate in both domestic and abroad. Thus, the present study calculated amount of movement of floating debris based on moving route monitoring results according to changes of effective rainfall and flow rate that are obtained by using SCS-CN method.

A design of transcendental function arithmetic unit for lighting operation of mobile 3D graphic processor (모바일 3차원 그래픽 프로세서의 조명처리 연산을 위한 초월함수 연산기 구현)

  • Lee, Sang-Hun;Lee, Chan-Ho
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.715-718
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    • 2005
  • Mobile devices is getting to include more functions according to the demand of digital convergence. Applications based on 3D graphic calculation such as 3D games and navigation are one of the functions. 3D graphic calculation requires heavy calculation. Therefore, we need dedicated 3D graphic hardware unit with high performance. 3D graphic calculation needs a lot of complicated floating-point arithmetic operation. However, most of current mobile 3D graphics processors do not have efficient architecture for mobile devices because they are based on those for conventional computer systems. In this paper, we propose arithmetic units for special functions of lighting operation of 3D graphics. Transcendental arithmetic units are designed using approximation of logarithm function. Special function units for lighting operation such as reciprocal, square root, reciprocal of square root, and power can be obtained. The proposed arithmetic unit has lower error rate and smaller silicon area than conventional arithmetic architecture.

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