• Journal of Biosystems Engineering
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• v.12 no.1
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• pp.45-52
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• 1987

In order to improve the thermal efficiency of an internal combustion engine, various ignition timing control systems were examined and the best one was chosen. The parts used for the systems were a microcomputer system with DAS, 8 bit output port (D-FLIP FLOP), three types of isolation circuit, two types of ignition timing pulse generator, three types of switching circuit and two types of high voltage ignition circuit. Most systems did not operate well due to the effects of electromagnetic waves and surge currents occurring when the ignition began or ended with resulting high voltage. The best ignition timing control system was found to be the combination of (microcomputer system)-(ignition timing pulse generator using step motor position control pick-up)-(switching circuit using TR logic)-(high voltage ignition circuit using CDI).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.2
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• pp.182-190
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• 2011

A amplitude modulation(AM) range measuring system utilizes the phase difference of the modulated envelope of the reflected signal to measure the distance. It is known that the AM system has a problem in accuracy due to antenna leakage signals and spurious reflection signals, but an AM range measurement system using an active reflector, which shifts the frequency bands, has been proposed in order to minimize the measurement errors due to spurious signals. In this paper, a new phase measurement module for the AM range measurement system, which enables to measure long distance with good accuracy, is proposed. The modulation frequency is alternatively selected between 8 and 1 MHz, and the measured distance range with this module is up to 150 m within 2 cm accuracy. A JK flip-flop circuit is used for higher phase accuracy, and an XOR circuit is used to cover long distance.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.63-73
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• 2015

This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.27-38
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• 2016

This work proposes a 12b 30MS/s 0.18um CMOS SAR ADC based on low-power composite switching with an active die area of $0.16mm^2$. The proposed composite switching employs the conventional $V_{CM}$-based switching and monotonic switching sequences while minimizing the switching power consumption of a DAC and the dynamic offset to constrain a linearity of the SAR ADC. Two equally-divided capacitors topology and the reference scaling are employed to implement the $V_{CM}$-based switching effectively and match an input signal range with a reference voltage range in the proposed C-R hybrid DAC. The techniques also simplify the overall circuits and reduce the total number of unit capacitors up to 64 in the fully differential version of the prototype 12b ADC. Meanwhile, the SAR logic block of the proposed SAR ADC employs a simple latch-type register rather than a D flip-flop-based register not only to improve the speed and stability of the SAR operation but also to reduce the area and power consumption by driving reference switches in the DAC directly without any decoder. The measured DNL and INL of the prototype ADC in a 0.18um CMOS are within 0.85LSB and 2.53LSB, respectively. The ADC shows a maximum SNDR of a 59.33dB and a maximum SFDR of 69.83dB at 30MS/s. The ADC consumes 2.25mW at a 1.8V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.75-82
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• 2000

In this paper, a new low power 16-bit ALU has been designed, fabricated and tested at the transistor level. The designed ALU performs 16 instructions and has a two-stage pipelined architecture. For the reduction of switched capacitance, the ELM adder of the proposed ALU is inactive while the logical operation is performed and P(propagation) block has a dual bus architecture. A new efficient P and G(generation) blocks are also proposed for the above ALU architecture. ELM adder, double-edge triggered register and the combination of logic style are used for low power consumption as well. As a result of simulations, the proposed architecture shows better power efficient than conventional architecture$^{[1,2]}$ as the number of logic operation to be performed is increased over that of arithmetic to logic operation to be performed is 7 to 3, compared to conventional architecture. The proposed ALU was fabricated with 0.6${\mu}m$ single-poly triple-metal CMOS process. As a result of chip test, the maximum operating frequency is 53MHz and power consumption is 33mW at 50MHz, 3.3V.

• The KIPS Transactions:PartA
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• v.10A no.3
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• pp.247-254
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• 2003

This paper describes a Delay Locked Loop (DLL) with low supply voltage and wide lock range for Synchronous DRAM which employs Double Data Rate (DDR) technique for faster data transmission. To obtain high resolution and fast lock-on time, a new type of phase detector is designed. The new counter and lock indicator structure are suggested based on the Dual-clock dual-data Flip Flop (DCDD FF). The DCDD FF reduces the size of counter and lock indicator by about 70%. The delay line is composed of coarse and fine units. By the use of fast phase detector, the coarse delay line can detect minute phase difference of 0.2 nsec and below. Aided further by the new type of 3-step vernier fine delay line, this DLL circuit achieves unprecedented timing resolution of 25psec. This DLL spans wide locking range from 500MHz to 500MHz and generates high-speed clocks with fast lock-on time of less than 5 clocks. When designed using 0.25 um CMOS technology with 1.8V supply voltage, the circuit consumes 32mA at 500MHz locked condition. This circuit can be also used for other applications as well, such as synchronization of high frequency communication systems.

• Journal of Life Science
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• v.25 no.4
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• pp.416-424
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• 2015

Pinosylvin is a stilbenoid found in the Pinus species. Pinosylvin at ~pM to ~nM concentrations induces cell proliferation, cell migration and anti-inflammatory activity in endothelial cells. However, it was recently reported that pinosylvin at high concentrations (50 to 100 μM) induces cell death in bovine aortic endothelial cells. In this study, we conducted a series of experiments to discover how pinosylvin at a high concentration (50 μM) induces endothelial cell death. Pinosylvin at the high concentration was shown to induce endothelial cell apoptosis through enhancing caspase-3 activity, flip-flop of phosphatidyl serine, and nuclear fragmentation. We found that pinosylvin at the high concentration additively increased caspase-3 activity enhanced by serum-starvation or treatment with 100 μM etoposide. We also determined that pinosylvin at the high concentration promoted activations of c-Jun N-terminal kinase (JNK) and endothelial nitric oxide synthetase (eNOS). We further ran a series of experiments to find out which signaling molecule plays a critical role in the pinosylvin-induced apoptosis. We finally found that SP-600125, a JNK inhibitor, had an inhibitory effect on the pinosylvin-induced endothelial cell death, but L-NAME, an eNOS inhibitor, had no effect. These data indicate that JNK is involved in the pinosylvin-induced apoptosis. Collectively, pinosylvin at high doses induces cell apoptosis via JNK activation.