• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2009년도 추계학술대회 논문집
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• pp.207-208
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• 2009

• 제어로봇시스템학회논문지
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• 제15권9호
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• pp.916-921
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• 2009

The technology to inspect and measure an inner structure of micro parts has become an important tool in the semi-conductor industrial field with the development of automation and precision manufacturing. Especially, the inspection skill on the inside of highly integrated electronic device becomes a key role in detecting defects of a completely assembled product. X-ray inspection technology has been focused as a main method to inspect the inside structure. However, there has been insufficient research done on the customized inspection technology for the flip-chip assembly due to the interior connecting part of flip chip which connects the die and PCB electrically through balls positioned on the die. In this study, therefore, it is implemented to detect shape error of flip chip bonding without damaging chips using an x-ray inspection system. At this time, it is able to monitor the solder bump shape by introducing an edge-extracting algorithm (exponential approximation function) according to the attenuating characteristic and detect shape error compared with CAD data. Additionally, the bonding error of solder bumps is automatically detectable by acquiring numerical size information at the extracted solder bump edges.

• 전자공학회논문지C
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• 제35C권3호
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• pp.1-15
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• 1998

In this paper, we propose a partial scan test method which can be applied to large VLSI designs. In this method, it is not necessary to hold neither scanned nor unscanned flip-flops during scan in, test application,or scan out. This test method requires almost identical design for testability modification and test wave form when compared to the full scan test method, and the method is applicable to large VLSI chips. The well known FAN algorithm has been modified to devise to sequential ATPG algorithm which is effective for the proposed test method. In addition, a partial scan algorithm which is effective for the proposed test method. In addition, a partial algorithm determined a maximal set of flip-flops which gives high fault coverage when they are unselected. The experimental resutls show that the proposed method allow as large as 20% flip-flops to remain unscanned without much decrease in the full scan fault coverage.

• Transactions on Electrical and Electronic Materials
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• 제9권1호
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• pp.33-37
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• 2008

This paper describes the development of a new $5.0{\times}3.2mm$ SAW filter bank which is consist of 12 L, C matching components and 4 SAW bare chips on PCB substrate with CSP technology. We improved the manufacturing cost by removing the ceramic package through direct flip bonding of $LiTaO_3$ SAW bare chip on PCB board after mounting L, C passive element on PCB board. After that we realized the hermitic sealing by laminating the epoxy film. To confirm the confidentiality and durability of the above method, we have obtained the optimum flip bonding & film laminating condition, and figured out material property and structure to secure the durability & moisture proof of PCB board. The newly developed super mini $5.0{\times}3.2mm$ filter bank shows the superior features than those of existing products in confidence, electrical, mechanical characters.

• 한국전기전자재료학회논문지
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• 제29권4호
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• pp.237-240
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• 2016

The improvement of irradiation intensity and irradiation uniformity is essential for large area and high power UVA light source application. In this study, large number of chips bonded by micro soldering technique were driven by low current, and current limiting diodes were configured to supply constant current to parallel circuits consisting of large number of series strings. The dimension of light source module circuit board was $350{\times}90mm^2$ and 16,650 numbers of 385 nm flip chip LEDs were used with a configuration of 90 parallel and 185 series strings. The space between LEDs in parallel and series strings were maintained at 1.9 mm and 1.0 mm distance, respectively. The size of the flip chip was $750{\times}750{\mu}m^2$ were used with contact pads of $260{\times}669{\mu}m^2$ size, and SAC (96.5 Sn/3.0 Ag/0.5 Cu) solder was used for flip chip bonding. The fabricated light source module with 7.5 m A supply current showed temperature rise of $66^{\circ}C$, whereas irradiation was measured to be $300mW/cm^2$. Inaddition, 0.23% variation of the constant current in each series string was demonstrated.

• 마이크로전자및패키징학회지
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• 제11권1호
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• pp.29-36
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• 2004

초 박형 실리콘 칩을 이용하여 실리콘 칩들을 포함한 모듈 전체가 굽힘이 자유로운 유연 패키징 기술을 구현하였으며 bending test와 FEA를 통해 초 박형 실리콘 칩의 기계적 거동을 살펴보았다. 초박형 실리콘 칩(t<30$\mu\textrm{m}$)은 표면손상의 가능성을 배제하기 위해 KOH및 TMAH둥을 이용한 화학적 thinning 방법을 이용하여 제작되었으며 열압착 방식에 의해 $Kapton^{Kapton}$에 바로 실장 되었다. 실리콘칩과 $Kapton^\circledR$ 기판간의 단차가 적기 때문에 전기도금 방식으로 전기적 결선을 이를 수 있었다. 이러한 방식의 패키징은 이러한 공정은 flip chip 공정에 비해 공정 간단하고 wire 본딩과 달리 표면 단차 적어서 연성회로 기판을 비롯한 인쇄회로기판의 표면뿐만 아니라 기판 자체에 삽입이 가능하여 패키징 밀도 증가를 기대할 수 있으며 실질적인 실장 가능면적을 극대화 할 수 있다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2004년도 ISMP Pb-free solders and the PCB technologies related to Pb-free solders
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• pp.1-26
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• 2004

The implementation of Pb-free solder technology is making good progress in electronic industry. Further understanding on fundamental issues on Pb-free solders/processes is required to reduce reliability risk factors of Pb-free solder joints. Several reliability issues including thermal fatigue, impact reliability, IMC growth, spalling, void formation are reviewed for Pb-free solder joints. Several applications of Pb-free technology are discussed, such as Pb-free, CBGA, CuCGA, flip chips, and wafer bumping by IMS.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2007년도 춘계학술대회B
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• pp.2449-2452
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• 2007

Hot spots on thin wafers of IC packages are becoming important issues in thermal and electrical engineering fields. To investigate these hot spots, we developed a Diode Temperature Sensor Array (DTSA) that consists of an array of 32 ${\times}$32 diodes (1,024 diodes) in a 8 mm ${\times}$ 8 mm surface area. To know specifically the hot spot temperature which is affected by the chip thickness and a generated power, we made the DTSA chips, which have 21.5 ${\mu}m$, 31 ${\mu}m$, 42 ${\mu}m$, 100 ${\mu}m$, 200 ${\mu}m$, and 400 ${\mu}m$ thickness using the CMP process. And we conducted the experiment using various heater power conditions (0.2 W, 0.3 W, 0.4 W, 0.5 W). In order to validate experimental results, we performed a numerical simulation. Errors between experimental results and numerical data are less than 4%. Finally, we proposed a correlation for the hot spot temperature as a function of the generated power and the wafer thickness based on the results of the experiment. This correlation can give an easy estimate of the hot spot temperature for flip chip packaging when the wafer thickness and the generated power are given.

• 한국공작기계학회논문집
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• 제16권6호
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• pp.168-174
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• 2007

A ceramic glass mold was developed for micro hot-embossing and replicated polymer parts are fabricated. The glass-ceramic micro mold could be fabricated with a laser process and a wet etching process and the fabrication time could be saved a lot. Various polymer micro structures can be obtained by hot-embossing. The process parameters such as ho-embossing temperatures or pressures were investigated and optimized. This process can be applied for fabrication of micro structures for flip-chips or micro fluidic channels for bio-engineering. The advantages and disadvantages of this process are discussed, too.

• Journal of Semiconductor Engineering
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• 제1권3호
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• pp.81-87
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• 2020

An instrumentation amplifier (IA) and an analog-to-digital converter (ADC) are essential circuit blocks for accurate and robust sensor readout systems. This paper introduces recent advances in radiation-hardening by design (RHBD) techniques applied for the sensor readout integrated circuits (IC), e.g., the three-op-amp IA and the successive-approximation register (SAR) ADC, operating against total ionizing dose (TID) and singe event effect (SEE) in harsh radiation environments. The radiation-hardened IA utilized TID monitoring and adaptive reference control to compensate for transistor parameter variations due to radiation effects. The radiation-hardened SAR ADC adopts delay-based double-feedback flip-flops to prevent soft errors which flips the data bits. Radiation-hardened IA and ADC were verified through compact model simulation, and fabricated CMOS chips were measured in radiation facilities to confirm their radiation tolerance.