• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.5C
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• pp.386-394
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• 2008

For digital holographic video system, it is important to generate digital hologram as fast as possible. This paper proposed a fixed-point method and fast generation method that can calculate the Fresnel hologram using operation of whole-coordinate recursive addition. To compute the digital hologram, 3D object is assumed to be a collection of depth-map point generated using a PC. Our algorithm can compute a phase on a hologram by recursive addition with fixed-point format at a high speed. When we operated this algorithm on a personal computer, we could maximally compute digital hologram about 70% faster than conventional method and about 30% faster than of [3]'s method.

• Journal of Korea Multimedia Society
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• v.18 no.11
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• pp.1289-1301
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• 2015

Pedestrian detection (PD) is an essential task in various applications and sliding window-based methods utilizing HOG (Histogram of Oriented Gradients) or HOG-like descriptors have been shown to be very effective for accurate PD. However, due to exhaustive search across images, PD methods based on sliding window usually require heavy computational time. In this paper, we propose a real-time PD method for embedded visual surveillance with fixed backgrounds. The proposed PD method employs HOG descriptors as many PD methods does, but utilizes selective search so that it can save processing time significantly. The proposed selective search is guided by restricting searching to candidate regions extracted from Adaptive Gaussian Mixture Model (AGMM)-based background subtraction technique. Moreover, approximate computation of HOG descriptor and implementation in fixed-point arithmetic mode contributes to reduction of processing time further. Possible accuracy degradation due to approximate computation is compensated by applying an appropriate one among three offline trained SVM classifiers according to sizes of candidate regions. The experimental results show that the proposed PD method significantly improves processing speed without noticeable accuracy degradation compared to the original HOG-based PD and HOG with cascade SVM so that it is a suitable real-time PD implementation for embedded surveillance systems.

• Proceedings of the IEEK Conference
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• 2000.11d
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• pp.81-84
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• 2000

Cellular automata are discrete dynamical systems whose behaviour is completely specified in terms of a local relation. If cellular automata convergence to fixed points, then it can be used to image processing. From the generalized Potts automata point of view, we propose in this paper a cellular automata technique for reducing image noise. To minimize blurring effect, an algorithm based on neighborhood median computation is Preferred. Experimental results are reported.

• Journal of the Chungcheong Mathematical Society
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• v.28 no.2
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• pp.243-249
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• 2015

Let X be a closed surface for which the Euler characteristic $_{\mathcal{X}}(X)$ is negative, and let $f:X{\rightarrow}X$ be a self-map that is not surjective. In this short paper, we prove that we can compute the Nielsen number of f, N(f), under some algebraic conditions.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1195-1201
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• 2005

This paper deals with procedures and results for teal time implementation of G.729 speech coder and channel coder including convolution codec, viterbi decoder, and interleaver using a fixed point DSP chip for radio communication systems. We described the method for real-time implementation based on integer simulation results and explained the implemented results by quality performance and required complexity for real-time operation. The required complexity was 24MIPS and 9MIPS in computational load, and 12K words and 4K words in execution code length for speech and channel. The functional evaluation was performed into two steps. The one was bit exact comparison with a fixed point C code, the other was executed by actual speech samples and error test vectors. Unlik other results such as individual implementation, We implemented speech and channel coders on a DSP chip with 160MIPS computation capability and 64 K words memory on chip. This results outweigh the conventional methods in the point of system complexity and implementation cost for radio communication system.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.1
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• pp.101-113
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• 1986

In this paper, a real-time pitch detector LPC vocoder as implemented on a high speed digital signal processor, NEC 7720, is described. The pitch detector was based mainly on the SIFT algorithm. The SIFT pitch detector consists primarily of a digital low pass filter, inverse filter, computation of autocorrelation, a peak picker, interpolation, V/UV defcision and a final pitch smoother. In our approach, modification, mainly on the V/UV decision and a final pitch smoother, was made to estimate more accurate pitches. An 16-bit fixed-point aithmatic was employed for all necessary computation and the simulated results were compared with the eye detected pitches obtained from real speech data. The pitch detector occupies 98.8% of the instruction ROM, 37% of the data ROM, and 94% of internal RAM and takes 15.2ms to estimate a pitch when an analysis frame is consisted of 128 sampled speech data. It is observed that the tested results were well agreed with the computer simulation results.

• Journal of Korea Multimedia Society
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• v.13 no.3
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• pp.417-429
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• 2010

Though background subtraction has been widely studied for last decades, it is still a poorly solved problem especially when it meets real environments. In this paper, we first address some common problems for background subtraction that occur in real environments and then those problems are resolved by improving an existing GMM-based background modeling method. First, to achieve low computations, fixed point operations are used. Because background model usually does not require high precision of variables, we can reduce the computation time while maintaining its accuracy by adopting fixed point operations rather than floating point operations. Secondly, to avoid erroneous backgrounds that are induced by high pedestrian traffic, static levels of pixels are examined using shot-time statistics of pixel history. By using a lower learning rate for non-static pixels, we can preserve valid backgrounds even for busy scenes where foregrounds dominate. Finally, to adapt rapid illumination changes, we estimated the intensity change between two consecutive frames as a linear transform and compensated learned background models according to the estimated transform. By applying the fixed point operation to existing GMM-based method, it was able to reduce the computation time to about 30% of the original processing time. Also, experiments on a real video with high pedestrian traffic showed that our proposed method improves the previous background modeling methods by 20% in detection rate and 5~10% in false alarm rate.

• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.6
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• pp.335-344
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• 2014

As a kind of 2D spatial coordinate transform, image warping is a basic image processing technique utilized in various applications. Though image warping algorithm is composed of relatively simple operations such as memory accesses and computations of weighted average, real-time implementations on embedded vision systems suffer from limited computational power because the simple operations are iterated as many times as the number of pixels. This paper presents a real-time implementation of a look-up table(LUT)-based image warping using an FPGA. In order to ensure sufficient data transfer rate from memories storing mapping LUT and image data, appropriate memory devices are selected by analyzing memory access patterns in an LUT-based image warping using backward mapping. In addition, hardware structure of a parallel and pipelined architecture is proposed for fast computation of bilinear interpolation using fixed-point operations. Accuracy of the implemented hardware is verified using a synthesized test image, and an application to real-time lens distortion correction is exemplified.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.31-39
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• 1998

This paper presents the design and implementation of a new multimedia fixed-point DSP (MDSP) core for portable multimedia applications. The MDSP instruction set is designed through the analysis of multimedia algorithms and DSP instruction sets. The MDSP architecture employs parallel processing techniques, such as SIMD and vector processing as well as DSP techniques. The instruction set can handle various data formats and MDSP can perform two MAC operations in parallel. The switching network and packing network can increase the performance by overlapping data rearrangement cycles with computation cycles. We have designed Verilog HDL models and the 0.6 $\mu\textrm{m}$ Samsung KG75000 SOG library is used. The total gate count is 68,831 and the clock frequency is 30 MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.49-59
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• 2008

SIFT(Scale Invariant Feature Transform) is an algorithm to extract vectors at pixels around keypoints, in which the pixel colors are very different from neighbors, such as vortices and edges of an object. The SIFT algorithm is being actively researched for various image processing applications including 3-D image constructions, and its most computation-intensive stage is a keypoint localization. In this paper, we develope a fixed-point model of the keypoint localization and propose its efficient hardware architecture for embedded applications. The bit-length of key variables are determined based on two performance measures: localization accuracy and error rate. Comparing with the original algorithm (implemented in Matlab), the accuracy and error rate of the proposed fixed point model are 93.57% and 2.72% respectively. In addition, we found that most of missing keypoints appeared at the edges of an object which are not very important in the case of keypoints matching. We estimate that the hardware implementation will give processing speed of $10{\sim}15\;frame/sec$, while its fixed point implementation on Pentium Core2Duo (2.13 GHz) and ARM9 (400 MHz) takes 10 seconds and one hour each to process a frame.