• Journal of KIISE:Computing Practices and Letters
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• v.16 no.11
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• pp.1136-1140
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• 2010

Esterel is an imperative synchronous language and its formal semantic based on finite state machine makes it easy to perform program analyses using automata. In this paper, we propose a syntax-driven automata generation rule. Because our rule intuitively expresses syntactic structure, it is very useful for other program analyses.

• Annual Conference of KIPS
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• 2002.04b
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• pp.1305-1308
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• 2002

기존의 많은 동기화 모델 중 EFSM(Extended Finite State Machine)기반 동기화 모델을 수정 보완한 MFSM(Modified Finite State Machine) 동기화 모델을 제안한다. MFSM 동기화 모델은 지역의 Host들이 원격지의 Host 와 멀티미디어 데이터를 주고받기 위해서 미디어 재 동기화를 위한 중간 서버를 두고 미디어간 동기화를 위한 Inter-media Synchronization 역할을 Sync Master과 Sync Slave로 나누어 기존 논문의 단점을 보완한다. 3GPP2 무선 이동통신 환경에서 다자간 영상회의를 위해 멀티미디어 데이터 송수신시에 미디어 동기화를 위해서 MRF(Media Resource Function)가 데이터를 중계하는 MFSM기반의 동기화 모델을 제안한다.

• The Transactions of the Korea Information Processing Society
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• v.2 no.2
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• pp.254-263
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• 1995

In this paper we discuss Moore and Mealy-model Time-stationary control schemes of pipelined data paths of Application Specific, Integrated Circuits (ASICs). We developed a method to synthesize both a Moore and a Mealy-style Finite State Machine(FSM) controller specifications given a pipelined data path with conditional branches. The control synthesis task consists of the generation of control specification and the FSM synthesis. The control specification procedure generates a FSM specification in the form of a state table. The different partitioning schemes are applied to each FSM controller so as to minimize the total area. Experimental results show the characteristics of the two different control styles and the effects of these two models on cost and performance.

• Journal of KIISE:Software and Applications
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• v.35 no.1
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• pp.12-21
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• 2008

As the usage of computer systems is increasing in our lives, the reliability and safely of these systems need to be thoroughly checked through the verification techniques. As a basic formalism for several modeling methods, the finite state machine (FSM) is widely used in specification and verification of system models. And there is a technique for ing internal events of FSM in order to effectively analyze the system. However, this technique does not handle the state explosion problem since it can be applied after completely generating all the state space of the system. In this research, we provide a new approach for efficiently representing concurrent properties of FSM, the slice model and provide an efficient transition reduction method based on the slice model. Our approach is effective in time and space perspective since it is peformed by partially generating the needed system states while the existing abstraction technique can be applied to all the system states.

• Proceedings of the Korean Nuclear Society Conference
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• 2001.10a
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• pp.80.2-80
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• 2001

• Journal of IKEEE
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• v.27 no.3
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• pp.273-279
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• 2023

The use of line memory is essential for image filtering in image processing hardware. After input data is stored in line memory, filtering is performed after synchronization to use the stored data. A sync generator is used for synchronization, and in the case of a conventional sync generator, the input sync signal is delayed by one row of the input image. If a signal delayed by two rows is required, it is necessary to connect two modules. This approach increases the size of the hardware and cannot be designed efficiently. In this paper, we propose a sync generator that generates multiple types of delayed signals by adding a finite state machine. The hardware design was coded in Verilog HDL, and performance is verified by applying it to image processing hardware using field programmable gate array board.

• Journal of Electrical Engineering and Technology
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• v.12 no.2
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• pp.718-725
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• 2017

The method of stator segmentation is generally taken to enhance the electromagnetic performance of surface-mounted permanent magnet (SPM) machine and reduce its production cost. Based on the model with single slot, the expressions of cogging torque in machine with uniform or non-uniform segmentations are deduced and the optimal combination is given. Moreover, this paper discusses a structured skewing method and put forward a novel stator structure model to reduce the cogging torque in segmented permanent magnet machine. The model can reduce the cogging torque amplitude by shifting a proper angle of slot-opening. The shifting angle formula for analysis can also be suitable for other permanent machine with segmented stator. Finally the results of finite element simulation are given to prove that the method is effective and feasible.

• Journal of the Korean Society for Precision Engineering
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• v.28 no.3
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• pp.265-274
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• 2011

This paper presents current state of the prediction simulator of structural characteristics of machinery equipment accuracy. Developed accuracy prediction simulator proceeds and estimates the structural analysis between the designer and simulator through the internet for convenience of designer. 3D CAD model which is input to the accuracy prediction simulator would simplified by the process of removing the small hole, fillet and chamfer. And the structural surface joints would be presented as the spring elements and damping elements for the structural analysis. The structural analysis of machinery equipment joints, containing rotary motion unit, linear motion unit, mounting device and bolted joint, are presented using Finite Element Method and their experiment. Finally, a general method is presented to tune the static stiffness at a rotation joint considering the whole machinery equipment system by interactive use of Finite Element Method and static load experiment.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.4
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• pp.2149-2170
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• 2017

Application-layer Distributed Denial-of-Service (DDoS) attack is one of the leading security problems in the Internet. In recent years, the attack strategies of application-layer DDoS have rapidly developed. This paper introduces a new attack strategy named Path Vulnerabilities-Based (PVB) attack. In this attack strategy, an attacker first analyzes the contents of web pages and subsequently measures the actual response time of each webpage to build a web-resource-weighted-directed graph. The attacker uses a Top M Longest Path algorithm to find M DDoS vulnerable paths that consume considerable resources when sequentially accessing the pages following any of those paths. A detection mechanism for such attack is also proposed and discussed. A finite-state machine is used to model the dynamical processes for the state of the user's session and monitor the PVB attacks. Numerical results based on real-traffic simulations reveal the efficiency of the attack strategy and the detection mechanism.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.4
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• pp.127-137
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• 1989

This paper describes hardware flow-chart and SDL-II, which are register-transfer level, to automate logic design. Hardware flow-chart specifies behavioral and structural charaterstics of generalized FSMs (Finite State Machine) usin the modified ASM (Algorithmic State Machnine) design techniques. SDL-II describes the hardware flow-chat which specifies the control and the data path of ASIC(Application Specific IC). Also many examples are enumerated to illustrate the features of hardware flow-chart and SDL-II.