• Proceedings of the Korea Information Processing Society Conference
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• 2010.04a
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• pp.966-968
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• 2010

컴퓨팅 자원의 확보가 용이해짐에 따라 이러한 자원을 최대한 활용하려는 시도가 늘어나고 있다. 시스템을 검사하는 정형적 기법으로써 많이 사용되고 있는 모델 체킹은 상태폭발 문제를 완화하기 위해서 여러 컴퓨팅 자원을 한꺼번에 사용하려는 연구가 이루어져 왔다. 하지만 이 기법 역시 여러 상태 모델들이 하나로 합쳐지면서 여전히 상태폭발 문제를 발생 시킨다. 본 논문에서는 이러한 문제가 나타나는 원인을 지적하고 이를 해결하기 위해 모델 체킹의 기본 요소인 새로운 병렬적 도달성 분석 기법을 제시한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.04a
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• pp.613-615
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• 2009

서비스 기반 아키텍쳐(SOA)는 최근에 많은 관심을 끌고 있다. SOA 는 독립된 컴포넌트 기반 소프트웨어 아키텍쳐로서 소프트웨어의 기능이 독립된 서비스로서 제공되는데 독립된 서비스를 다양하게 구성하여 복잡한 또는 새로운 기능의 서비스를 제공할 수 있다는 장점을 가진다. 하지만 QoS 또는 Safety 를 보장할 수 없다는 한계점을 가지고 있으며 우리는 동적 시맨틱스를 사용하여 이를 극복할 수 있는 방법을 제안하고자 한다. 동적 시맨틱스는 Finite State Machine 과 시맨틱스를 결합한 형태로 구성되며 서비스의 기능적 요소를 시맨틱스로 표현하고 서비스의 비기능적 요소를 천이가 가능한 상태들로 표현하자는 것이다. 이러한 동적 시맨틱스를 상용하여 서비스의 사용자 또는 복합서비스의 설계자는 서비스의 성능을 예상할 수 있으며 이를 통하여 보다 신뢰도 높은 서비스를 제공할 수 있을 것으로 예상한다.

• Journal of the Korean Institute of Intelligent Systems
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• v.23 no.2
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• pp.120-125
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• 2013

This paper proposes a goal oriented action planning method that plans the behaviors of computer generated forces and a replanning method that replans new actions when the situations are changed in war game. This new method provides good expression because it is flexible and can do more realized description unlike the conventional finite state machines. As a result, proposed method has an advantage that it can describe the behaviors of computer generated forces as those of real soldier. However, since it is not deterministic it has some difficulties in analysing the decision processing of behaviors and making the computer generated forces do some specific actions. We employed combat plane models of air forces in order to verify the feasibility of our method. Finally, we could find that our method produced very similar behaviors to those of a real soldier. This paper describes our planning method, experimental results, and future works.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.5
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• pp.300-310
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• 2007

The Session Initiation Protocol (SIP) is one of the major protocols used in call-setup over IP telephony. The SIP-signaled calls use many-sided states according to a request of user. In this paper, we suggest seven states and some events that help developers to design and implement new applications efficiently. And they enable an object-oriented design of the system. If you design the call-setup procedure only by the processing model suggested in RFC 3261 over commercial network, a fatal error may occur in the system because of heavy data traffic or unpredicted exception cases. However, according to the suggested seven states, if they are predefined events in the current system state, the standardized processing routine is executed. Otherwise, they can be processed by the exception routine in system. All event processing routines are designed and implemented using Finite State Machine (FSM).

• Journal of KIISE:Software and Applications
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• v.30 no.3_4
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• pp.212-218
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• 2003

State invariant is a property that holds in every reachable state. It can be used not only in understanding and analyzing complex software systems, but it can also be used for system verifications such as checking safety, liveness, and consistency. For these reasons, there are many vital researches for deriving state invariant from finite state machine models. In previous works every reachable state is to be considered to generate state invariant. Thus it is likely to be too complex for the user to understand. This paper seeks to answer the question `how to simplify state invariant\ulcorner`. Since the complexity of state invariant is strongly dependent upon the size of states to be considered, so the smaller the set of states to be considered is, the shorter the length of state invariant is. For doing so, we let the user focus on some interested scopes rather than a whole state space in a model. Computation Tree Logic(CTL) is used to specify scopes in which he/she is interested. Given a scope in CTL, mixed reachability analysis is used to find out a set of states inside it. Obviously, a set of states calculated in this way is a subset of every reachable state. Therefore, we give a weaker, but comprehensible, state invariant.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.61-71
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• 2014

As the occupancy rate of the flash memory increases in the storage media market for the embedded system and the semi-conductor industry grows, the demand and supply of flash memory is increasing by a big margin. They are especially used in large quantity in the smart phones, tablets, PC, SSD and Soc(System on Chip) etc. The flash memory is divided into the NOR type and NAND type according to the cell arrangement structure and the NAND type is divided into the SLC(Single Level Cell) and MLC(Multi Level Cell) according to the number of bits that can be stored in each cell. Many tests have been performed on NOR type such as BIST(Bulit-In Self Test) and BIRA(Bulit-In Redundancy Analysis) etc, but there is little study on the NAND type. For the case of the existing BIST, the test can be proceeded using external equipments like ATE of high price. However, this paper is an attempt for the improvement of credibility and harvest rate of the system by proposing the BIST for the MLC NAND type flash memory of Finite State Machine structure on which the pattern test can be performed without external equipment since the necessary patterns are embedded in the interior and which uses the MLC NAND March(x) algorithm and pattern which had been proposed for the MLC NAND type flash memory.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.12
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• pp.1914-1919
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• 2021

With the development of advanced industries, research on image processing hardware is essential, and timing verification at the gate level is required for actual chip operation. For FPGA-based verification, DDR3 memory interface was previously applied. But recently, as the FPGA specification has improved, DDR4 memory is used. In this case, when a previously used memory interface is applied, the timing mismatch of signals may occur and thus cannot be used. This is due to the difference in performance between CPU and memory. In this paper, the problem is solved through state optimization of the existing interface system FSM. In this process, data read speed is doubled through AXI Data Width modification. For actual case analysis, ZC706 using DDR3 memory and ZCU106 using DDR4 memory among Xilinx's SoC boards are used.

• The Transactions of the Korea Information Processing Society
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• v.4 no.2
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• pp.552-562
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• 1997

This paper proposes a formal method on confromance testing for INAP(AIN) test sequence generation by optimization technique.In order to implement and prove the dffectiveness of the proposed method,we specify the SRSM of INAP protocol SRF in SDL and generate I/O FSM by using our S/W tool. We generate an opti-mal test sequence by applying our method our method to this reference I/O FSM. We prove experimentally that the length of the generated test sequence by our method is more effective and shorter(i.e 32% improved)than the one geverated by UIO method,and estimate that The test coverage space of our test sequence is larger that of UIO method.

• Journal of KIISE:Computing Practices and Letters
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• v.5 no.5
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• pp.595-610
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• 1999

This paper presents a visual simulation tool for verification and validation(V&V) of design implications of the Object Behavior Chart developed in accordance with the existing real-time object's behavior design method. This tool can simulates the dynamic interactions using the executable simulation machine, that is EFSM(Extended Finite State Machine) and can detect various logical and temporal errors in the visual object behavior charts before a concrete implementation is made. For this, a LOTOS prototype specification is automatically generated from the visual Object Behavior Chart, and is translated into an EFSM. This system is implemented in Visual C++ version 4.2 and currently runs on PC Windows 95 environment. For simulation purpose, LOTOS was chosen because of it's excellence in specifying communication protocols. Our research contributes to the support tools for seamlessly integrating methodology-based graphical models and formal-based simulation techniques, and also contributes to the automated V&V of the Visual Models.

• The KSFM Journal of Fluid Machinery
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• v.11 no.5
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• pp.50-56
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• 2008

Metal cutting operations involve generation of heat due to friction between the tool and the pieces. This heat needs to be carried away otherwise it creates white spots. To reduce this abnormal heat cutting fluid is used. Cutting fluid also has an important role in the lubrication of the cutting edges of machine tools and the pieces they are shaping, and in sluicing away the resulting swarf. As a cutting fluid, water is a great conductor of heat but is not stable at high temperatures, so to improve stability an emulsion type mixed fluid with water and oil is often used. It is pumped over the cutting site of cutting machines as a state of atomized water droplet coated with oil by using jet. In this paper, to develop cutting fluid supplying nozzle to obtain ultra thin oil film for coating water droplet, a numerical analysis of three dimensional mixed fluid Jet through multi-stage nozzle was carried out by using a finite volume method. Jet flow characteristics such as nozzle exit velocity, development of mixing region, re-entrance and jet intensity were analyzed. Detailed mixing process of fluids such as air, water and oil in the nozzle were also investigated. It is easy to understand complex flow pattern in multi-stage nozzle. Important flow Information for advance design of cutting fluid supplying nozzle was drawn.