• The Transactions of the Korea Information Processing Society
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• v.2 no.2
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• pp.254-263
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• 1995

In this paper we discuss Moore and Mealy-model Time-stationary control schemes of pipelined data paths of Application Specific, Integrated Circuits (ASICs). We developed a method to synthesize both a Moore and a Mealy-style Finite State Machine(FSM) controller specifications given a pipelined data path with conditional branches. The control synthesis task consists of the generation of control specification and the FSM synthesis. The control specification procedure generates a FSM specification in the form of a state table. The different partitioning schemes are applied to each FSM controller so as to minimize the total area. Experimental results show the characteristics of the two different control styles and the effects of these two models on cost and performance.

• Nuclear Engineering and Technology
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• v.48 no.4
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• pp.1047-1057
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• 2016

Design engineering process for field programmable gate array (FPGA)-based reactor trip functions are developed in this work. The process discussed in this work is based on the systems engineering approach. The overall design process is effectively implemented by combining with design and implementation processes. It transforms its overall development process from traditional V-model to Y-model. This approach gives the benefit of concurrent engineering of design work with software implementation. As a result, it reduces development time and effort. The design engineering process consisted of five activities, which are performed and discussed: needs/systems analysis; requirement analysis; functional analysis; design synthesis; and design verification and validation. Those activities are used to develop FPGA-based reactor bistable trip functions that trigger reactor trip when the process input value exceeds the setpoint. To implement design synthesis effectively, a model-based design technique is implied. The finite-state machine with data path structural modeling technique together with very high speed integrated circuit hardware description language and the Aldec Active-HDL tool are used to design, model, and verify the reactor bistable trip functions for nuclear power plants.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.6
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• pp.33-42
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• 2010

This research propose a practical guidance system considering ocean currents in real sea operation. Optimality of generated path is not an issue in this paper. Way-points from start point to possible goal positions are selected by experienced human supervisors considering major ocean current axis. This paper also describes the implementation of a precise underwater navigation solution using multi-sensor fusion technique based on USBL, GPS, DVL and AHRS measurements in detail. To implement the precise, accurate and frequent underwater navigation solution, three strategies are chosen. The first one is the heading alignment angle identification to enhance the performance of standalone dead-reckoning algorithm. The second one is that absolute position is fused timely to prevent accumulation of integration error, where the absolute position can be selected between USBL and GPS considering sensor status. The third one is introduction of effective outlier rejection algorithm. The performance of the developed algorithm is verified with experimental data of mine disposal vehicle and deep-sea ROV.