• Journal of Korea Society of Digital Industry and Information Management
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• v.16 no.2
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• pp.1-9
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• 2020

Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.6
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• pp.313-319
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• 2019

Finite field operations have played an important role in error correcting codes and cryptosystems. Recently, the necessity of efficient computation processing is increasing for security in cyber physics systems. Therefore, efficient implementation of finite field arithmetics is more urgently needed. These operations include addition, multiplication, division and inversion. Addition is very simple and can be implemented with XOR operation. The others are somewhat more complicated than addition. Among these operations, multiplication is the most important, since time-consuming operations, such as exponentiation, division, and computing multiplicative inverse, can be performed through iterative multiplications. In this paper, we propose a multiplexer based parallel computation algorithm that performs Montgomery multiplication over finite field using redundant basis. Then we propose an efficient multiplexer based semi-systolic multiplier over finite field using redundant basis. The proposed multiplier has less area-time (AT) complexity than related multipliers. In detail, the AT complexity of the proposed multiplier is improved by approximately 19% and 65% compared to the multipliers of Kim-Han and Choi-Lee, respectively. Therefore, our multiplier is suitable for VLSI implementation and can be easily applied as the basic building block for various applications.

• Journal of Ocean Engineering and Technology
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• v.20 no.2 s.69
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• pp.1-7
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• 2006

This paper, presents a comparison between numerical analysis and field test on a real offshore platform in Bohai Bay, China. This platform is a steel jacket offshore platform with vertical piles. The field testing under wave-induced force and wind force etc. was conducted, in order to obtain the dynamic parameters of the structure, including the frequencies of the jacket platform, as well as the corresponding damping ratios and mode shapes. The natural excitation technology (NexT) combined with eigensystem realization algorithm (ERA) and the peak picking (PP) method in frequency domain are carried out for modal parameter indentification under operational conditions. The three-dimeansional finite element model (FEM) is constructed by ANSYS and analytical modal analysis is performed to generate modal parameters. The analytical results were compared with experimental results. A good agreement was achieved between the finite element and analysis and field test results. It is further demonstrated that the numerical and experimental modal analysis provide a comprehensive study on the dynamic properties of the jacket platform. According to the analysis results, the modal parameters identification under ambient excitation can calibrate finite element model of the jacket platform structures, or can be used for the structural health monitoring system.

• Journal of Mechanical Science and Technology
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• v.17 no.12
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• pp.1835-1843
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• 2003

This paper introduces the development of the caliper system for a geometry PIG (Pipeline Inspection Gauge). The objective of the caliper system is to detect and measure dents, wrinkles, and ovalities affect the pipe structural integrity. The developed caliper system consists of a finger arm, an anisotropic permanent magnet, a back yoke, pins, pinholes and a linear hall effect sensor. The angle displacement of the finger arm is measured by the change of the magnetic field in sensing module. Therefore the sensitivity of the caliper system mainly depends on the magnitude of the magnetic field inside the sensing module. In this research, the ring shaped anisotropic permanent magnet and linear hall effect sensors were used to produce and measure the magnetic field. The structure of the permanent magnet, the back yoke and pinhole positions were optimized that the magnitude of the magnetic field range between a high of 0.1020 Tesla and a low of zero by using three dimensional nonlinear finite element methods. A simulator was fabricated to prove the effectiveness of the developed caliper system and the computational scheme using the finite element method. The experimental results show that the developed caliper system is quite efficient for the geometry PIG with good performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.1
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• pp.57-67
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• 2005

Fast scalar multiplication of points on elliptic curve is important for elliptic curve cryptography applications. In order to vary field sizes depending on security situations, the cryptography coprocessors should support variable length finite field arithmetic units. To determine the effective variable length finite field arithmetic architecture, two well-known curve scalar multiplication algorithms were implemented on FPGA. The affine coordinates algorithm must use a hardware division unit, but the projective coordinates algorithm only uses a fast multiplication unit. The former algorithm needs the division hardware. The latter only requires a multiplication hardware, but it need more space to store intermediate results. To make the division unit versatile, we need to add a feedback signal line at every bit position. We proposed a method to mitigate this problem. For multiplication in projective coordinates implementation, we use a widely used digit serial multiplication hardware, which is simpler to be made versatile. We experimented with our implemented ECC coprocessors using variable length finite field arithmetic unit which has the maximum field size 256. On the clock speed 40 MHz, the scalar multiplication time is 6.0 msec for affine implementation while it is 1.15 msec for projective implementation. As a result of the study, we found that the projective coordinates algorithm which does not use the division hardware was faster than the affine coordinate algorithm. In addition, the memory implementation effectiveness relative to logic implementation will have a large influence on the implementation space requirements of the two algorithms.

• Communications of the Korean Mathematical Society
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• v.33 no.3
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• pp.759-765
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• 2018

We use the finite method developed by C. Athanasiadis based on Crapo-Rota's theorem to give a complete formula for the characteristic polynomial of hyperplane arrangements ${\mathcal{J}}_n$ consisting of the hyperplanes $x_i+x_j=1$, $x_k=0$, $x_l=1$, $1{\leq}i,j,k,l{\leq}n$.

• Bulletin of the Korean Mathematical Society
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• v.51 no.4
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• pp.1087-1100
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• 2014

We present an accurate and efficient numerical method for solving the Black-Scholes equation. The method uses an adaptive grid technique which is based on a far-field boundary position and the Peclet condition. We present the algorithm for the automatic adaptive grid generation: First, we determine a priori suitable far-field boundary location using the mathematical model parameters. Second, generate the uniform fine grid around the non-smooth point of the payoff and a non-uniform grid in the remaining regions. Numerical tests are presented to demonstrate the accuracy and efficiency of the proposed method. The results show that the computational time is reduced substantially with the accuracy being maintained.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.1
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• pp.11-18
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• 2017

Finite field arithmetic has been extensively used in error correcting codes and cryptography. Low-complexity and high-speed designs for finite field arithmetic are needed to meet the demands of wider bandwidth, better security and higher portability for personal communication device. In particular, cryptosystems in GF($2^m$) usually require computing exponentiation, division, and multiplicative inverse, which are very costly operations. These operations can be performed by computing modular AB multiplications or modular $AB^2$ multiplications. To compute these time-consuming operations, using $AB^2$ multiplications is more efficient than AB multiplications. Thus, there are needs for an efficient $AB^2$ multiplier architecture. In this paper, we propose a low latency Montgomery $AB^2$ multiplier using redundant representation over GF($2^m$). The proposed $AB^2$ multiplier has less space and time complexities compared to related multipliers. As compared to the corresponding existing structures, the proposed $AB^2$ multiplier saves at least 18% area, 50% time, and 59% area-time (AT) complexity. Accordingly, it is well suited for VLSI implementation and can be easily applied as a basic component for computing complex operations over finite field, such as exponentiation, division, and multiplicative inverse.

• Journal of Korea Society of Digital Industry and Information Management
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• v.18 no.1
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• pp.1-9
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• 2022

Galois field arithmetic is important in error correcting codes and public-key cryptography schemes. Hardware realization of these schemes requires an efficient implementation of Galois field arithmetic operations. Multiplication is the main finite field operation and designing efficient multiplier can clearly affect the performance of compute-intensive applications. Diverse algorithms and hardware architectures are presented in the literature for hardware realization of Galois field multiplication to acquire a reduction in time and area. This paper presents a low complexity semi-systolic multiplier to facilitate parallel processing by partitioning Montgomery modular multiplication (MMM) into two independent and identical units and two-level systolic computation scheme. Analytical results indicate that the proposed multiplier achieves lower area-time (AT) complexity compared to related multipliers. Moreover, the proposed method has regularity, concurrency, and modularity, and thus is well suited for VLSI implementation. It can be applied as a core circuit for multiplication and division/exponentiation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.35-42
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• 2007

The finite-field division can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field division takes much time to compute. In this paper, we propose a radix-4 systolic divider on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed divide, is mathematically developed and new counter structure is proposed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for YLSI design. Compared to the bit-parallel, bit-serial and digit-serial dividers, the proposed divider has relatively effective high performance and low cost. We design and synthesis $GF(2^{193})$ finite-field divider using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.