• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2007년도 춘계학술대회 논문집
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• pp.551-552
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• 2007

• 마이크로전자및패키징학회지
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• 제18권3호
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• pp.67-74
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• 2011

Keys to high wiring density semiconductor packages include flip-chip bonding and build-up substrate technologies. The current issues are the establishment of a fine pitch flip-chip bonding technology and a low coefficient of thermal expansion (CTE) substrate technology. In particular, electromigration and thermomigration in fine pitch flipchip joints have been recognized as a major reliability issue. In this paper, electromigration and thermomigration in Cu/Sn-3Ag-0.5Cu (SAC305)/Cu flip-chip joints and electromigration in Cu/In/Cu flip chip joints are investigated. In the electromigration test, a large electromigration void nucleation at the cathode, large growth of intermetallic compounds (IMCs) at the anode, a unique solder bump deformation towards the cathode, and the significantly prolonged electromigration lifetime with the underfill were observed in both types of joints. In addition, the effects of crystallographic orientation of Sn on electromigration were observed in the Cu/SAC305/Cu joints. In the thermomigration test, Cu dissolution was accelerated on the hot side, and formation of IMCs was enhanced on the cold side at a thermal gradient of about $60^{\circ}C$/cm, which was lower than previously reported. The rate of Cu atom migration was found comparable to that of electromigration under current conditions.

• Transactions on Electrical and Electronic Materials
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• 제14권2호
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• pp.63-66
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• 2013

This paper describes the highly productive process technologies of microprobe arrays, which were used for a probe card to test a Dynamic Random Access Memory (DRAM) chip with fine pitch pads. Cantilever-type microprobe arrays were fabricated using conventional micro-electro-mechanical system (MEMS) process technologies. Bonding material, gold-tin (Au-Sn) paste, was used to bond the Ni-Co alloy microprobes to the ceramic space transformer. The electrical and mechanical characteristics of a probe card with fabricated microprobes were measured by a conventional probe card tester. A probe card assembled with the fabricated microprobes showed good x-y alignment and planarity errors within ${\pm}5{\mu}m$ and ${\pm}10{\mu}m$, respectively. In addition, the average leakage current and contact resistance were approximately 1.04 nA and 0.054 ohm, respectively. The proposed highly productive microprobes can be applied to a MEMS probe card, to test a DRAM chip with fine pitch pads.

• 마이크로전자및패키징학회지
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• 제11권1호
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• pp.21-28
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• 2004

Polytetrafluoroethylene (PTFE/Teflon ) 인쇄회로기판용 미세 피치 솔더 범프 형성을 위해 dry film photoresist (DFR)를 photolithography 공정에 적용하였다. DFR lamination을 위한 test board는 폭 100$\mu\textrm{m}$와 두께 18$\mu\textrm{m}$의 copper line들이 100-200$\mu\textrm{m}$의 간격으로 배열된 형태로 디자인하였다. 15$\mu\textrm{m}$의 두께를 갖는 DFR을 hot roll laminator를 사용하여 lamination 온도와 속도를 변화시켜가면서 lamination 공정 실험을 수행하였다. 실험 결과, PTFE 인쇄회로기판에 DFR을 lamination하는 공정의 최적 조건은 lamination 온도 $150^{\circ}C$, 속도 약 0.63cm/s였다. UV exposure 및 development 공정을 거쳐 저융점 솔더 재료인 인듐을 증착하였다. DFR 박리 순서에 따른 두 가지 다른 reflow 공정을 통해 최소 지름 50$\mu\textrm{m}$, 최소 피치 100$\mu\textrm{m}$를 갖는 인듐 솔더 범프를 형성하였다.

• 마이크로전자및패키징학회지
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• 제13권2호
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• pp.21-26
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• 2006

NCA의 물성이 미세피치 Chip on glass (COG) 접합부의 신뢰성에 미치는 영향을 연구하였다. Si 위에 Sn을, 유리기판 위에 In을 열증발 방법으로 증착하고 lift-off 방법을 이용하여 $30{\mu}m$ 피치를 가지는 솔더범프를 형성하였으며 열압착 방법으로 $120^{\circ}C$에서 In 범프와 Sn 범프를 접합하였다. 접합할 때 세 종류의 Non conductive adhesive (NCA)를 적용하였다. 신뢰성은 $0^{\circ}C$와 $100^{\circ}C$ 사이로 열충격시험을 2000회까지 실시하여 평가하였다. 4단자 저항측정법을 이용하여 접합부의 저항을 측정하였다. 필러의 양이 증가할수록 열충격시험 후 접합부의 저항이 가장 적게 증가하여 신뢰성이 우수하였다. 필러의 양이 증가할수록 NCA의 열팽창이 작아지기 때문이다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제41회 하계 정기 학술대회 초록집
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• pp.277-277
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• 2011

디스플레이의 기술발전에 의해 대면적 고해상도의 LCD가 제작되어 왔다. 이에 따라 LCD 점등검사를 위한 Probe Unit의 기술 또한 급속도로 발전하고 있다. 고해상도에 따라 TFT LCD pad가 미세피치화 되어가고 있으며, panel의 검사를 위한 Probe 또한 30 um 이하의 초미세피치를 요구하고 있다. 따라서, 초미세 pitch의 LCD panel의 점등검사를 위한 Probe Unit의 개발이 시급하가. 본 연구에서는 30 um 이하의 미세피치의 Probe block을 위한 Slit wafer의 식각 공정 조건을 연구하였다. Si 공정에서 식각율과 식각깊이에 따른 profile angle의 목표를 설정하고, 식각조건에 따라 이 두 값의 변화를 관측하였다. 식각실험으로 Si DRIE 장비를 이용하여, chamber 압력, cycle time, gas flow, Oxygen의 조건에 따라 각각의 단면 및 표면을 SEM 관측을 통해 최적의 식각 조건을 찾고자 하였다. 식각율은 5um/min 이상, profile angle은 $90{\pm}1^{\circ}$의 값을 목표로 하였다. 이 때 최적의 식각조건은 Etching : SF6 400 sccm, 10.4 sec, passivation : C4F8 400 sccm, 4 sec의 조건이었으며, 식각공정의 Coil power는 2,600 W이었다. 이러한 조건의 공정으로 6 inch Si wafer에 공정한 결과 균일한 식각율 및 profile angle 값을 보였으며, oxygen gas를 미량 유입함으로써 식각율이 균일해짐을 알 수 있었다. 결론적으로 최적의 Slit wafer 식각 조건을 확립함으로써 Probe Unit을 위한 Pin 삽입공정 또한 수율 향상이 기대된다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.183-184
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• 2007

A 40 Gb/s transimpedance amplifier IC was designed and fabricated with a InP/InGaAs HBTs technology. In this study, we interconnect 40Gbps trans impedance amplifier IC to a duroid substrate by a flip chip bonding instead of conventional wire bonding for interconnection. For flip chip bonding, we developed fine pitch bump with the $70{\mu}m$ diameter and $150{\mu}m$ pitch using WLP process. To study the effect of WLP, electrical performance was measured and analyzed in wafer and package module using WLP. The Small signal gains in wafer and package module were 7.24 dB and 6.93dB respectively. The difference of small signal gain in wafer and package module was 0.3dB. This small difference of gain is due to the short interconnection length by bump. The characteristics of return loss was under -10dB in both wafer and module. So, WLP process can be used for millimeter wave GaAs MMIC with the fine pitch pad and duroid substrate can be used in flip chip bonding process.

• 소성∙가공
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• 제19권8호
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• pp.474-479
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• 2010

Newly suggested hybrid LED package can reduce the number of LED processes and enhance light efficacy in virtue of its integrated optical patterns. Square-type pyramid pattern was chosen for the integrated optical pattern in this study, and it was proved that the pattern enhances illuminance about three times and luminance about two and half times by optical simulation. Square-type pyramid patterns of 0.02mm height and 0.04mm pitch were successively machined on a copper mold which is necessary for imprinting the integrated pattern. Hybrid LED package with integrated optical pattern will be manufactured with ultra-fine machined mold in future study.

• 소음진동
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• 제8권2호
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• pp.346-352
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• 1998

This paper presents actuating characteristics of an asymmetric high-speed optical pick-up fine actuator that can be installed in a small area such as a notebook personal computer. In the asymmetric actuator four points (mass center, actuation center, supporting point of wire suspension on a bobbin, and optical axis) are not coincident so that the proposed actuator suspension reveals undesirable suspension resonance in the pitch and yaw direction. Lumped parameter dynamic model in each direction is used to investigate the driving characteristics with respect to relative location of the four points. Some of desired design directions toward reducing resonance peaks are suggested by using sensitivity information. In order to avoid undesirable resonance, at least supporting point on the obbin must be located in the middle of the mass and actuation center of the asymmetric pick-up actuator.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.1787-1790
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• 2005

We have developed satellite devices for fine attitude control of the Science & Technology Satellite-2 (STSAT-2) scheduled to be launched in 2007. The analog sun sensors which have been continuously developed since the 1990s are not adequate for satellites which require fine attitude control system. From the mission requirements of STSAT-2, a compact, fast and fine digital sensor was proposed. The test of the fine attitude determination for the pitch and roll axis, though the main mission of STSAT-2, will be performed by the newly developed FDSS. The FDSS use a CMOS image sensor and has an accuracy of less than 0.01degrees, an update rate of 20Hz and a weight of less than 800g. A pinhole-type aperture is substituted for the optical lens to minimize the weight while maintaining sensor accuracy by a rigorous centroid algorithm. The target process speed is obtained by utilizing the Field Programmable Gate Array (FPGA) in acquiring images from the CMOS sensor, and storing and processing the data. This paper also describes the analysis of the optical performance for the proper aperture selection and the most effective centroid algorithm.