• JSTS:Journal of Semiconductor Technology and Science
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• 제12권1호
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• pp.88-98
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• 2012

In this paper, the relationship between the bandwidth (BW) and power efficiency of a source follower based (SFB) filter is quantitatively analyzed, and a design methodology for a SFB filter for optimized BW - power consumption is introduced. The proposed design methodology achieves a maximum BW at a target quality (Q) factor for the given power consumption constraint by controlling design factors individually. In order to achieve the target BW from the maximized BW, a tuning method is introduced. Through the proposed design methodology, a fourth order Butterworth filter was implemented in 0.18 ${\mu}m$ CMOS technology. The measured BW, power consumption, and IIP3 are 100 MHz, 33 ${\mu}W$, and 9 dBm, respectively. Compared with other filter structures, the measured results show high BW - power efficiency.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.118-121
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• 2004

The cutoff frequency of a LC output filter for Dynamic Voltage Restorers (DVR) limits the control bandwidth of a DVR system and the attenuation factor against the inverter switching ripples. For a selected cutoff frequency of a LC output filter, infinite number of L-C combinations is possible. Although different L-C combination has different filter characteristics, the filter design on L-C combination has been depended on field experiences without clear analysis. This paper proposes a design criterion and design examples for the L-C filter combination considering the control characteristics and the size of DVRs. An experimental DVR system based on the proposed LC output filter design methodology is built and tested.

• 한국통신학회:학술대회논문집
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• 한국통신학회 1983년도 추계학술발표회논문집
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• pp.56-60
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• 1983

There has been a great amount of interest in the design of digital filters with low sensitivity to coefficient variations. Especiaily the wave digital filter modeled after analog IC ladder filter has been studied to have low-cocfficient-sensitivity properties. This paper examined the design of the wave digital filter and how the sensitivity and roundoff noise porperty arises. As a result of computer simulation the implementation of the digital filter was possible with a lower coefficient word length comparing with the conventional cascade structure.

• 한국공작기계학회논문집
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• 제17권6호
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• pp.111-117
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• 2008

An automation process of filter unit is presented for the application of the assembling procedure and dry furnace work. By that automation procedure, it is expected to enhance working environment such as reducing laboring load, harmful gas, and burning scald. Furthermore, this automation process also minimizes via standardization of manufacturing process so that it may increase productivity and reliability. An automation process of filter unit is presented for the application of the assembling procedure and dry furnace work. Filter automation process also gives a good quality and productivity by simplifying to only one line from the complicated process such as filter cutting$\rightarrow$ adhering$\rightarrow$fabricating in a very small space. It is found that a new conceptual design of dry furnace shows the better quality like uniform heat distribution compared to the conventional design. It is also found that the present design gives a better working environment by adding cooling system.

• 전자공학회논문지
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• 제49권11호
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• pp.141-148
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• 2012

Oversampling 기법을 사용한 analog-to-digital (A/D) 컨버터에서 샘플링 된 신호의 signal bandwidth를 낮추어 주기 위해 데시메이션 필터가 사용된다. 본 논문은 sigma-delta ADC에 사용될 수 있는 저전력 4 단 32 bit 데시메이터 필터 디자인을 제안한다. 디지털 데시메이션 필터는 CIC(cascaded integrator-comb) filter와 세 개의 half-band FIR filter로 이루어져 있다. 전력소모를 최소화하기 위하여 CIC filter에는 pipeline구조가 사용되었고, FIR 필터의 multiplier 구조를 최적화하기 위하여 Canonic Signed Digit (CSD) 코드가 사용되었다. 130nm CMOS 공정으로 설계 자동화 CAD 도구를 사용하여 타이밍, 면적, 전력소모를 최적화하여 98.304 MHz 주파수에서 697 uW의 전력을 소모면서 32 bit, 192 kHz 아웃풋을 낼 수 있다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 A
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• pp.259-261
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• 1996

In this paper, active input filter for power factor correction(PFC) circuit employing ripple arrent and voltage cancellation is proposed to reduce filter's size and cost, and to make filter design easy. Switching ripple current and voltage can be sensed through the secondary windings of filter inductor. Single stage passive filter can achieve high order filter characteristics by using active ripple current and voltage cancellation technique. Conventional high order passive filter and its problems are suggested. Analysis of active filter and design procedure are detailed. Simulation result is presented to verify high order filter characteristics of proposed scheme.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권3호
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• pp.261-273
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• 2016

Reconfigurable finite impulse response (FIR) filters whose filter coefficients and filter order change dynamically during run-time play an important role in the software defined radio (SDR) systems, multi-channel filters, and digital up/down converters. However, there are not many reports on such reconfigurable designs which can support dynamic variation of filter order and filter coefficients. The purpose of this paper is to provide an architectural solution for the FIR filters to support run-time variation of the filter order and filter coefficients. First, two straightforward designs, namely, (i) single-MAC based design and (ii) full-parallel design are presented. For large variation of the filter order, two designs based on (iii) folded structure and (iv) fast FIR algorithm are presented. Finally, we propose (v) high throughput design which provides significant advantage in terms of hardware and/or time complexities over the other designs. We compare complexities of all the five structures, and provide the synthesis results for verification.

• Journal of Electrical Engineering and Technology
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• 제12권5호
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• pp.1945-1954
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• 2017

In recent years, several LCL filter design methods for different converter topologies have been published, many of which use analytical expressions to calculate the ideal converter AC voltage harmonic spectrum. This paper presents the LCL filter design methodology but the focus is on presentation and validation of the non-iterative filter design method for a grid-connected three-phase two-level PWM-VSC. The developed method can be adapted for different converter topologies and PWM algorithms. Furthermore, as a starting point for the design procedure, only the range of PWM carrier frequencies is required instead of an exact value. System nonlinearities, usually omitted from analysis have a significant influence on VSC AC voltage harmonic spectrum. In order to achieve better accuracy of the proposed procedure, the system nonlinear model is incorporated into the method. Optimal filter parameters are determined using the novel cost function based on higher frequency losses of the filter. An example of LCL filter design for a 40 kVA grid-connected PWM-VSC has been presented. Obtained results have been used to construct the corresponding laboratory setup and measurements have been performed to verify the proposed method.

• 한국산업융합학회 논문집
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• 제24권5호
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• pp.581-587
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• 2021

In recent years, contamination of drinking water sources has emerged as a serious social problem, such as a large number of impurities in tap water or groundwater or the supply of suitable water due to rust of pipes. Although the government and public institutions are implementing various measures to protect water sources, they cannot improve water quality in a short period of time because of the enormous cost involved. Therefore, in recent years, preference has been given to a device that converts tap water, which is hard water, into soft water by installing a separate water softener at the faucet from which tap water is discharged. However, the existing filtration device has a problem that filtration performance is gradually lowered when impurities accumulate in the filter, requiring continuous filter replacement. In this study, the optimal design of the filter housing was performed to develop a water softener that can be washed when impurities accumulate on the filter inside the water softener connected to the faucet. For optimal design of the filter housing, fluid and fluid-structural interaction analysis were performed on the design pressure to determine the shape and thickness of the housing, and design review was performed through prototype.

• Journal of Power Electronics
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• 제18권4호
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• pp.1178-1189
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• 2018

In grid-connected voltage-source inverters (VSIs), when compared with a simple inductive L filter, the LCL filter has a better performance in attenuating the high frequency harmonics caused by the pulse-width modulation of power switches. However, the resonance peaks generated by the filter inductors and capacitors can make a system unstable. In terms of simplicity and filter design cost, a passive damping method is generally preferred. However, its high power loss and degradation in high frequency harmonic attenuation are significant demerits. In this paper, a mathematical design solution for a passive LCL filter to derive filter parameters suppressing the high frequency current harmonics to 0.3% is proposed. The minimum filter inductance can be obtained to reduce the size of the filter. Furthermore, a minimum damping resistance design considering a current controller is analyzed for a stable closed-loop system. The proposed design method is verified by experimental results using a 5-kW three-phase prototype inverter.