• 전기학회논문지
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• 제66권1호
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• pp.100-106
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• 2017

In this paper, we propose a parallel optimization method of Aho-Corasick (AC) algorithm and Parallel Failureless Aho-Corasick (PFAC) algorithm using Open Computing Language (OpenCL) on Field Programmable Gate Array (FPGA). The low throughput of string matching engine causes the performance degradation of network process. Recently, many researchers have studied the string matching engine using parallel computing. FPGA's vendors offer a parallel computing platform using OpenCL. In this paper, we apply the AC and PFAC algorithm on DE1-SoC board with Cyclone V FPGA, where the optimization that considers FPGA architecture is performed. Experiments are performed considering global id, local id, local memory, and loop unrolling optimizations using PFAC algorithm. The performance improvement using loop unrolling is 129 times greater than AC algorithm that not adopt loop unrolling. The performance improvements using loop unrolling are 1.1, 0.2, and 1.5 times greater than those using global id, local id, and local memory optimizations mentioned above.

• 한국정보통신학회논문지
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• 제17권5호
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• pp.1089-1094
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• 2013

본 논문에서는 모바일 디스플레이장치에 필요한 MDDI(Mobile Display Digital Interface) 프로토콜 패킷생성방법을 소프트웨어로 구현하는 것을 제안한다. 최소한의 하드웨어 구성을 가지며, 소프트웨어를 이용하여 MDDI 프로토콜 패킷을 생성한다. 이의 구현을 위해 고속 마이크로프로세와 FPGA(Field-Programmable Gate Array)로 하드웨어를 설계하였다. 소프트웨어로 생성한 패킷은 FPGA를 통해 LVDS(Low-Voltage Differential Signaling) 신호로 변환되어 출력된다. 제안하는 방식의 장점은 다양한 패킷을 소프트웨어로 쉽게 만들 수 있다는 것이다. 단점은 패킷전송에 걸리는 시간이 기존에 제안된 방식보다 빠르지 않았다. 이는 향후 개선되어야 할 과제로 남았다.

• 대한방사선기술학회지:방사선기술과학
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• 제36권2호
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• pp.157-163
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• 2013

2차원 방향으로 납을 이동하여 방사선 세기를 조절하는 기존의 다엽콜리메이터와는 다른 방식으로 고안 된 3차원 콜리메이터를 개발하였다. 3차원 콜리메이터는 복잡한 기하학적 구조에 방사선 조사에 있어 실시간으로 선량을 변화 할 수 있다. 3차원 콜리메이터는 정육면체 구조로 이를 구성하는 각각의 복셀화된 콜리메이터는 모터와 납으로 연결되어 있다. 각각의 프레임은 컴퓨터로 코딩된 FPGA 신호를 회로에 전달하여 계획대로 개별적으로 움직일 수 있다. 여러 가지 복잡한 기하학적 구조를 몬테칼로 시뮬레이션을 이용하여 결과를 도출하고 직접 실험한 결과를 비교 분석 하였다.

• Nuclear Engineering and Technology
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• 제50권6호
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• pp.860-868
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• 2018

This article presents a new design of earthquake instrumentation that is suitable for quick decision-making after the seismic event at the nuclear power plant (NPP). The main objective of this work is to ensure more availability of the NPP by expediting walk-down period when the seismic wave is incident. In general, the decision-making to restart the NPP after the seismic event requires more than 1 month if an earthquake exceeds operating basis earthquake level. It affects to the plant availability significantly. Unnecessary shutdown can be skipped through quick assessments of operating basis earthquake, safe shutdown earthquake events, and damage status to structure, system, and components. Multidecision parameters such as cumulative absolute velocity, peak ground acceleration, Modified Mercalli Intensity Scale, floor response spectrum, and cumulative fatigue are discussed. The implementation scope on the field-programmable gate array platform of this work is limited to cumulative absolute velocity, peak ground acceleration, and Modified Mercalli Intensity. It can ensure better availability of the plant through integrated decision-making process by automatic assessment of NPP structure, system, and components.

• 한국항행학회논문지
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• 제24권4호
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• pp.285-290
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• 2020

본 논문에서는 텔레메트리 시스템에 적용하기 위한 PLL 기반의 시각동기 알고리즘을 제시하고 FPGA 로직을 구현하였다. 텔레메트리 시스템에서 대형 비행체의 경우 각각의 분산 획득 장치들을 통해 상태정보를 계측하여 실시간으로 비행 상태를 분석해야하므로 정밀도 향상을 위한 장치 및 시스템 간의 시각 동기의 중요성이 커지고 있다. 이 때문에 시각동기 기법으로 타 시각동기 방법보다 복잡도가 적고, 동기를 위한 추가적인 메시지 전송을 최소화하여 데이터 처리에 적은 시간이 소요되는 PLL 기반의 시각동기 알고리즘을 제안하였다. 타당성을 확인하기 위해 python 시뮬레이션을 수행하였으며 최종적으로 FPGA 내에 VHDL 로직을 구현하여 시각 동기 성능을 확인하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 하계학술대회 논문집 A
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• pp.325-326
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• 2004

전력선통신(PLC: Power Line Communication)은 기존의 전기선을 이용하여 별도의 전용선 설치 없이 통신이 가능한 기술로서 효율적인 PLC 통신을 위해서는 가장 기본적인 기저대역의 송, 수신부상 의 원활한 데이터 전송이 이루어져야 한다. 본 논문에서는 확산대역방식의 PLC통신시스템의 수신부의 핵심모듈인 정합필터를 HDL(hardware description language)을 이용한 디지털 하드웨어인 에 위한 디지털 하드웨어인 FPGA(Field Programmable Gate Array)클 이용하여 구현하였다. 즉, 본 논문에서는 BPSK(Binary Phase Shift Keying) 변조 및 256칩 확산코드를 이용한 확산변조파형에 대한 디지털 정합필터를 FPGA로 구현하고 상관특성을 확인함으로서 모의실험상의 파형과 구현된 하드웨어상의 상관파형이 일치함을 확인하였다.

• Journal of Information Processing Systems
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• 제15권2호
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• pp.374-385
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• 2019

This paper presents an optimal implementation of a Daubechies-based pipelined discrete wavelet packet transform (DWPT) processor using finite impulse response (FIR) filter banks. The feed-forward pipelined (FFP) architecture is exploited for implementation of the DWPT on the field-programmable gate array (FPGA). The proposed DWPT is based on an efficient transpose form structure, thereby reducing its computational complexity by half of the system. Moreover, the efficiency of the design is further improved by using a canonical-signed digit-based binary expression (CSDBE) and advanced functional sharing (AFS) methods. In this work, the AFS technique is proposed to optimize the convolution of FIR filter banks for DWPT decomposition, which reduces the hardware resource utilization by not requiring any embedded digital signal processing (DSP) blocks. The proposed AFS and CSDBE-based DWPT system is embedded on the Virtex-7 FPGA board for testing. The proposed design is implemented as an intellectual property (IP) logic core that can easily be integrated into DSP systems for sub-band analysis. The achieved results conclude that the proposed method is very efficient in improving hardware resource utilization while maintaining accuracy of the result of DWPT.

• 시스템엔지니어링학술지
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• 제14권2호
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• pp.41-48
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• 2018

This paper describes the systems engineering development process for the Departure from Nucleate Boiling Ratio (DNBR) algorithm using FPGA. Current Core Protection Calculator System (CPCS) requirement and DNBR logic are analyzed in the reverse engineering phase and the new FPGA based DNBR algorithm is designed in the re-engineering phase. FPGA based DNBR algorithm is developed by VHSIC Hardware Description Language (VHDL) in the implementation phase and VHDL DNBR software is verified in the software Verification & Validation phase. Test cases are developed to perform the software module test for VHDL software modules. The APR 1400 simulator is used to collect the inputs data in 100%, 75%, and 50% reactor power condition. Test input signals are injected to the software modules following test case tables and output signals are compared with the expected test value. Minimum DNBR value from developed DNBR algorithm is validated by KEPCO E&C CPCS development facility. This paper summarizes the process to develop the FPGA-based DNBR calculation algorithm using systems engineering approach.

• 반도체디스플레이기술학회지
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• 제18권1호
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• pp.59-64
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• 2019

Recently, time synchronous has become important for satellite launch control facilities, multiple thermal power plants, and power system facilities. Information from time synchronous at each of these industrial sites requires time synchronization to control or monitor the system with correlation. In this paper, IRIG-B codes, which can be used for time synchronous, are used as specifications in IRIG standard 200-16. Signals from IRIG-B120 (Analog), IRIG-B000 (Digital), and one PPS are output from GPS receiver. Using the signal from IRIG-B120 (Analog), it passes through the signal from the analog amplifier and generates one PPS signal using the field-programmable gate array. The FPGA is used cyclone EPM570T100I5N. According to IEEE regulations, the error of one PPS is specified within 1us, but in this paper, the error is within 100ns. The output of the one PPS signal was then compared and tested against the one PPS signal on the GPS receiver to verify accuracy and reliability. In addition, the proposed time synchronous is simple to construct and structure, easy to implement, and provides high time precision compared to typical time synchronous. The output of the one PPS signals and IRIG-B000 signal will be used in many industry sectors.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제14권12호
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• pp.4648-4663
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• 2020

This paper proposes the Lempel-Ziv 4(LZ4) compression accelerator optimized for scale-out servers in data centers. In order to reduce CPU loads caused by compression, we propose an accelerator solution and implement the accelerator on an Field Programmable Gate Array(FPGA) as heterogeneous computing. The LZ4 compression hardware accelerator is a fully pipelined architecture and applies 16 dictionaries to enhance the parallelism for high throughput compressor. Our hardware accelerator is based on the 20-stage pipeline and dictionary architecture, highly customized to LZ4 compression algorithm and parallel hardware implementation. Proposing dictionary architecture allows achieving high throughput by comparing input sequences in multiple dictionaries simultaneously compared to a single dictionary. The experimental results provide the high throughput with intensively optimized in the FPGA. Additionally, we compare our implementation to CPU implementation results of LZ4 to provide insights on FPGA-based data centers. The proposed accelerator achieves the compression throughput of 639MB/s with fine parallelism to be deployed into scale-out servers. This approach enables the low power Intel Atom processor to realize the Hadoop storage along with the compression accelerator.