• 정보저장시스템학회:학술대회논문집
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• 2005.10a
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• pp.53-55
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• 2005

The surface potential variations are measured, according to the enhanced measuring speed and voltage sensitivity, using an active device, such as a field effect transistor $(FET)^{1-3}$. In this study, the surface potential was mapped in the patterned $SiO_2$ medium at room temperature. An improved FET-tip cantilever, which has a source, a drain, and an n- channel, was used in this study. The potential images were analyzed both in the contact mode and the non-contact mode, using only a pre-amplifier system instead of a lock-in the amplifier.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.71-71
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• 2010

최근 나노선의 우수한 전기적, 광학적 특성을 다양한 종류의 전자소자, 광소자, 그리고 센서에 응용하는 연구가 활발히 진행되고 있다. 그 중 $SnO_2$ 나노선은 n-type의 전기특성과 우수한 광 특성을 보이며, 전자소자, 광소자 뿐 아니라 다양한 종류의 가스 센서 제작에 널리 사용되고 있다. 본 연구에서는 화학기상증착법 (Chemical Vapor Deposition)으로 $SnO_2$ 나노선을 성장하여 전계방출효과 트랜지스터 (field effect transistor: FET)를 제작하여 전기적 특성을 측정하였다. 나노선의 성장 조건 (온도와 산소 유량) 에 따른 나노선의 구조, 화학조성, 전기적 특성을 체계적으로 조사하였다. 산소의 유량이 낮을 때는 온도에 따라 나노선의 크기와 전기 특성에 변화가 없었으나, 산소의 유량을 높이면 온도에 따라 나노선의 두께와 전기적 특성이 크게 변화하였다. 본 연구에서는 특히, FET 구조에서 on/off current ratio 가 $10^5$ 이상으로 매우 높은 나노선 제작이 가능하였다. 전기적 특성과 나노선의 결정구조, 화학적 조성을 함께 비교하여 성장 메커니즘을 이해하고자 한다.

• Journal of Sensor Science and Technology
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• v.9 no.2
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• pp.106-112
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• 2000

A FET-type reference electrode(REFET) is an effective method to eliminate typical problems with ISFET(ion sensitive field-effect transistor) such as drift, temperature, light-dependence and miniaturization of reference electrode. However, it is difficult to make the highly reliable REFET with excellent long-term stability and reproducibility. In this paper, an ion-blocking membrane was applied to the REFET for the PET-type electrolyte sensors(pH, pNa-ISFET). The fabricated REFET indicated the stable sensitivity (55.4 mV/pH, 53.5 mV/decade) and good linearity in the pH and pNa measurement. In the measurement, ISFET/Pt/REFET configuration showed excellent stability and reproducibility.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.4
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• pp.265-275
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• 2010

In this work, reliable methodology for device design is presented. Based on this method, the underlap length has been optimized for minimizing the gateinduced drain leakage (GIDL) in a 22-nm node 4-terminal (4-T) silicon-on-insulator (SOI) fin-shaped field effect transistor (FinFET) by TCAD simulation. In order to examine the effects of underlap length on GIDL more realistically, doping profile of the source and drain (S/D) junctions, carrier lifetimes, and the parameters for a band-to-band tunneling (BTBT) model have been experimentally extracted from the devices of 90-nm channel length as well as pnjunction test element groups (TEGs). It was confirmed that the underlap length should be near 15 nm to suppress GIDL effectively for reliable low standby power (LSTP) operation.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.221-225
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• 2003

The MFIS-FET(Field Effect Transistor) devices using $BLT/Y_2O_3$ buffer layer on p-Si(100) substrates were fabricated by the Sol-Gel method and conventional memory processes. The crystal structure, morphologies and electrical properties of prepared devices were investigated by using various measuring techniques. From the C-V(capacitance-voltage) data at 5V, the memory window voltage of the $Pt/BLT/Y_2O_3/si$ structure decreased from 1.4V to 0.6V with increasing the annealing temperature from $700^{\circ}C\;to\;750^{\circ}C$. The drain current (Ic) as a function of gate voltages $(V_G)$ for the $MFIS(Pt/BLT/Y_2O_3/Si(100))-FET$ devices at gate voltages $(V_G)$ of 3V, 4V and 5V, the memory window voltages increased from 0.3V to 0.8V as $V_G$ increased from 3V to 5V.

• Journal of Sensor Science and Technology
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• v.2 no.1
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• pp.35-40
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• 1993

A FET(field effect transistor) type lipid sensor was fabricated uy immobilizing lipase enzyme on the gate of pH-ISFET($SiO_{2}/Si_{3}N_{4}$). A water soluble polymer, polyvinyl alcohol(PVA) was modified with 1-methyl-4-(formyl-styryl) pyridinium methosulfate(SbQ) to give a photosensitive membrane(PVA-SbQ) in which lipase was immobilized. The optimum photolithographic conditions were ; spin coating speed $5,000{\sim}6,000$ rpm. UV exposure time $20{\sim}30$ seconds, developing time in water $30{\sim}40$ seconds, and vacuum drying time 45 min. at room temperature with the suspension containing PVA-SbQ aqueous solution(SbQ 1mol%, 10 wt %) $200{\mu}L$, bovine serum albumin (BSA) 7.5 mg, and lipase 10 mg. The lipid sensor showed good linear calibration curve in the range of $10{\sim}100$ mM triacetin as a lipid sample.

• Journal of IKEEE
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• v.23 no.2
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• pp.704-709
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• 2019

In this paper, the electrical characteristics of tunneling field effect transistor(TFET) was studied for different annealing conditions. The TFET samples annealed using hydrogen forming gas(4 %) and Deuterium($D_2$) forming gas(4 %). All the measurements were conducted in noise shielded environment. The results show that subthreshold slope(SS) decreased by 33 mV/dec after annealing process compared to before annealing. Under various temperature range, the noise is improved by average of 31.2 % for 10 atm Deuterium gas at $V_G=3V$ condition. It is also noticed that, post metal annealing with $D_2$ gas reduces the noise by average of 30.7 % at $I_D=100nA$ condition.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.585-593
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• 2015

In the nanoscale regime, many multigate devices are explored to reduce their size further and to enhance their performance. In this paper, design of a novel device called, Triple Material Surrounding Gate Tunnel Field effect transistor (TMSGTFET) has been developed and proposed. The advantages of surrounding gate and tunnel FET are combined to form a new structure. The gate material surrounding the device is replaced by three gate materials of different work functions in order to curb the short channel effects. A 2-D analytical modeling of the surface potential, lateral electric field, vertical electric field and drain current of the device is done, and the results are discussed. A step up potential profile is obtained which screens the drain potential, thus reducing the drain control over the channel. This results in appreciable diminishing of short channel effects and hot carrier effects. The proposed model also shows improved ON current. The excellent device characteristics predicted by the model are validated using TCAD simulation, thus ensuring the accuracy of our model.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.05a
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• pp.177-180
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• 2004

In this study, we report a novel encapsulation method for longevity of an organic thin-film transistor (OTFT) using pentaceneby means of an adhesive multiplayerincluded Al film. For encapsulation of OTFTs, the Al film adhered onto the OTFT in a dry nitrogen atmosphere using a proper adhesive. A lifetime, which was defined as the time necessary to reduce mobility to 2% of initial mobility value, was observed from the typical $I_{D-VD}$ characteristics of the field-effect transistor (FET). The initial field effect mobility ${\mu}$ was measured to be $2.0{\times}10^{-1}\;cm^2/Vs$. The characterization was maintained for long times in air. No substantial degeneration occurred. The performance and the stability are probably due to the encapsulation effect.

• Proceeding of EDISON Challenge
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• 2016.03a
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• pp.292-294
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• 2016

이황화몰리브덴을 활용한 전계효과트랜지스터(Field Effect Transistor)는 채널 물질의 우수한 특성으로 차세대 저전력 고성능 스위치와 광전소자로 주목받고있다. Underlap 게이트 구조에서 게이트 길이(L_G), 절연체 두께(T), 절연체 상대유전율(${\varepsilon}_r$)에 따라 변화하는 소자특성을 분석하여 저전력 고성능 $MoS_2$ 전계효과트랜지스터를 위한 게이트 구조 최적화방법을 모색하였다. EDISON simulator 중 Tight-binding NEGF 기반 TMD FET 소자 성능 및 특성 해석용 S/W를 활용하여 게이트 구조에 따른 게이트 전압 - 드레인 전류 상관관계(transfer characteristic)를 얻고, Y-function method를 이용하여 채널 유효전하이동도(Effective Mobility), Sub-threshold Swing, on/off 전류비(on/off current ratio)를 추출하여 비교 분석하였다. 시뮬레이션으로 추출한 소자의 최대 채널 유효전하이동도는 $37cm^2V^{-1}s^{-1}$, on/off 전류비는 $10^4{\sim}10^5$, Sub-threshold Swing은 ~38mV/dec 수준을 보였다.