• Journal of Electrical Engineering and Technology
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• v.10 no.3
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• pp.1169-1173
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• 2015

This paper presents vertical carbon nanotube (CNT) field effect transistors (FETs). For the first time, the author successfully fabricated vertical CNT-based FETs on an anodized aluminum oxide (AAO) template by using atomic layer deposition (ALD). Single walled CNTs were vertically grown and aligned with the vertical pores of an AAO template. By using ALD, a gate oxide material (Al₂O₃) and a gate metal (Au) were centrally located inside each pore, allowing the vertical CNTs grown in the pores to be individually gated. Characterizations of the gated/vertical CNTs were carried and the successful gate integration with the CNTs was confirmed.

• Journal of IKEEE
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• v.20 no.3
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• pp.220-225
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• 2016

In this paer, low on-resistance and high-power trench gate MOSFET (Metal-Oxide-Silicon Field Effect Transistor) incorporating current sensing FET (Field Effect Transistor) is proposed and evaluated. The trench gate power MOSFET was fabricated with $0.6{\mu}m$ trench width and $3.0{\mu}m$ cell pitch. Compared with the main switching MOSFET, the on-chip current sensing FET has the same device structure and geometry. In order to improve cell density and device reliability, self-aligned trench etching and hydrogen annealing techniques were performed. Moreover, maintaining low threshold voltage and simultaneously improving gate oxide relialility, the stacked gate oxide structure combining thermal and CVD (chemical vapor deposition) oxides was adopted. The on-resistance and breakdown voltage of the high density trench gate device were evaluated $24m{\Omega}$ and 100 V, respectively. The measured current sensing ratio and it's variation depending on the gate voltage were approximately 70:1 and less than 5.6 %.

• Journal of the Korean Vacuum Society
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• v.17 no.3
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• pp.199-203
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• 2008

The effects of surface treatment by $O_2$ plasma on the Bio-FETs were investigated by using the pseudo-MOSFETs on the SOI substrates. After a surface treatment by $O_2$ plasma with different RF powers, the current-voltage and field effect mobility of pseudo-MOSFETs were measured by applying back gate bias. The subthreshold characteristics of pseudo-MOSFETs were significantly degraded with increase of RF power. Additionally, a forming gas anneal process in 2 % diluted $H_2/N_2$ ambient was developed to recover the plasma process induced surface damages. A considerable improvement of the subthreshold characteristics was achieved by the forming gas anneal. Therefore, it is concluded that the pseudo-MOSFETs are a powerful tool for monitoring the surface treatment of Bio-FETs and the forming gas anneal process is effective for improving the electrical characteristics of Bio-FETs.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.482-491
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• 2012

In the present work, comprehensive investigation of the ambipolar characteristics of two silicon (Si) tunnel field-effect transistor (TFET) architectures (i.e. p-i-n and p-n-p-n) has been carried out. The impact of architectural modifications such as heterogeneous gate (HG) dielectric, gate drain underlap (GDU) and asymmetric source/drain doping on the ambipolar behavior is quantified in terms of physical parameters proposed for ambipolarity characterization. Moreover, the impact on the miller capacitance is also taken into consideration since ambipolarity is directly related to reliable logic circuit operation and miller capacitance is related to circuit performance.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.11a
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• pp.30.2-30.2
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• 2009

본 연구에서는 stamping법을이용하여 절연막에 실리콘 나노와이어를 embed시킨 field-effect transistor(FET) 소자의 전기적 특성에 대하여 분석하였다. Stamping법은 나노와이어를 이용한 소자를 제작하는데 있어 쉽고 경제적인 방법으로 최근 많이 사용되고 있는데, 이 방법을 이용하여 나노와이어를 절연막에 embed 시켰다. 이때, 사용한 실리콘 나노와이어는 무전해 식각법을 통하여 합성하였다. 식각 시간을 조절하여 나노와이어의 길이가 $100{\mu}m$ 정도가 되도록 하였고, 나노와이어의 지름은 정제를 통하여 20 ~ 200nm내로 조절하였다. FET 소자의 게이트 절연막은가장 일반적으로 사용되는 SiO2 (200nm)와 고분자 절연막으로 잘 알려진 poly-4-vinylphenol(PVP)를 사용하였다. 실리콘 나노와이어의 전기적 특성을 각각 SiO2무기 절연막에서의 non-embedded상태, PVP 유기 절연막에서의 embedded 상태에서 비교분석 하였다. 전기적 특성은 I-V 측정을 통하여 Ion/Ioff ratio, 이동도, subthreshold swing, threshold voltage값을 평가하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.630-634
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• 2016

We report the computer aided design results for a GaSb/InAs broken-gap gate all around nanowire tunneling FET (TFET). In designing, the semi-empirical tight-binding (TB) method using $sp3d5s^*$ is used as band structure model to produce the bulk properties. The calculated band structure is cooperated with open boundary conditions (OBCs) and a three-dimensional $Schr{\ddot{o}}dinger$-Poisson solver to execute quantum transport simulators. We find an device configuration for the operation voltage of 0.3 V which exhibit desired low sub-threshold swing (< 60 mV/dec) by adopting receded gate configuration while maintaining the high current characteristic ($I_{ON}$ > $100 {\mu}A/{\mu}m$) that broken-gap TFETs normally have.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.273-273
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• 2010

Recently, extensive research on hetero-junction arrays has been reported owing to its unique band gaps dissimilar to that of homo-junctions. These hetero-junction devices can be used in laser, solar cells, and various sensors. We report on the facile method to fabricate SWCNTs/SnO2 nanowires hetero-junction arrays on flexible polyimide substrate. Each SWCNT field effect transistor (FET) and SnO2 nanowire FET exhibits the purely p- and n-type charactersistics with ohmic contact properties. Such formed pn-junctions showed rectification behaviors reproducibly with a rectification ratio of ${\sim}3{\times}103$ at 1 V and ideality factors about 12. The pn-junctions also showed a good gate modulation behavior.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.268-268
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• 2010

단일벽 탄소 나노튜브(SWCNT)는 그 뛰어난 전기적, 물리적 특성 때문에 반도체 공정에 있어서 중요한 p-type 채널 물질로 꼽히고 있다. 본 연구에서는 SWCNT를 성장하여 이를 이용한 전계효과 트랜지스터를 제작하고 또한, 부분적인 폴리머의 코팅으로 타입을 변화하는 연구를 보이고자 한다. Ferritin용액을 DI-water에 2000배 희석하여 SiO2 기판 위에 뿌린 뒤 Methanol을 이용하여 기판 표면에 촉매가 붙어있게 한다. 이 기판을 $900^{\circ}C$로 가열하여 유기물질을 제거한 뒤 화학 기상 증착(Chemical Vapor Deposition)방법으로 SWCNT를 성장하게 된다. 이렇게 성장된 SWCNT는 촉매의 농도에 비례하는 밀도를 가지게 되며 이 위에 전극을 증착하고 back-gate를 설치하여 FET를 제작한다. 메탈릭한 SWCNT는 breakdown 공정을 통하여 제거한 뒤, 전자 농도가 높은 NADH를 전체적으로 코팅을 한다. NADH는 기존의 다른 폴리머(polyethyleneimine: PEI)에 비교하여 코팅 후 전자 제공 효과가 크며 그 성질의 재현성이 높고 공기 중에서 안정성을 유지하는 능력이 있다. 이러한 NADH의 코팅으로 n-type으로의 SWCNT FET를 제작하였으며 type conversion 현상을 이용하면 국부적인 NADH의 코팅으로 homojunction-diode의 제작 등 다양한 소자의 제작에 적용될 것으로 예상한다.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.197-197
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• 2012

Device 제작에 사용된 graphene은 일반적인 lithography 공정에서 resist residue에 의한 오염을 피할 수 없으며 이로 인하여 graphene의 pristine한 성질을 잃어버린다. 본 연구에서는 graphene을 저밀도의 argon inductively coupled plasma (Ar-ICP)를 통해 처리함으로서 graphene based back-gated field effect transistor (G-FET)의 특성변화를 유도한 결과에 대해서 보고한다. Argon capacitively coupled plasma (Ar-CCP)은 에 노출된 graphene은 강한 ion bombardment energy로 인하여 쉽게 planar C-C ${\pi}$ bonding (bonding energy: 2.7 eV)이 breaking되어 graphene의 defect이 발생되었다. 하지만 우리의 경우 저밀도의 Ar-ICP가 적용될 때 graphene의 defect이 제한되며 이와 동시에 contamination 만을 제거할 수 있었다. 소자의 전기적 측정 (Gsd-Vbg)을 통하여 contamination으로 인하여 p-doping된 graphene은 pristine 상태로 회복되었으며 mobility도 회복됨이 확인되었다. Ar-ICP를 이용한 graphene cleaning 방법은 저온공정, 대면적 공정, 고속공정을 모두 만족시키며 thermal annealing, electrical current annealing을 대체하여 graphene 기반 소자를 생산함에 있어 쉽고 빠르게 적용할 수 있는 강점이 있다.

• 정보저장시스템학회:학술대회논문집
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• 2005.10a
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• pp.56-58
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• 2005

To illustrate an application of the field effect transistor (FET) structure, this study suggests a new cantilever, using atomic force microscopy (AFM), for sensing surface potentials in nanoscale. A combination of the micro-electromechanical system technique for surface and bulk and the complementary metal oxide semiconductor process has been employed to fabricate the cantilever with a silicon-on-insulator (SOI) wafer. After the implantation of a high-ion dose, thermal annealing was used to control the channel length between the source and the drain. The basic principle of this cantilever is similar to the FET without a gate electrode.