• ETRI Journal
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• 제37권1호
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• pp.107-117
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• 2015

This paper presents an energy-efficient (low power) prime-field hyperelliptic curve cryptography (HECC) processor with uniform power draw. The HECC processor performs divisor scalar multiplication on the Jacobian of genus 2 hyperelliptic curves defined over prime fields for arbitrary field and curve parameters. It supports the most frequent case of divisor doubling and addition. The optimized implementation, which is synthesized in a $0.13{\mu}m$ standard CMOS technology, performs an 81-bit divisor multiplication in 503 ms consuming only $6.55{\mu}J$ of energy (average power consumption is $12.76{\mu}W$). In addition, we present a technique to make the power consumption of the HECC processor more uniform and lower the peaks of its power consumption.

• ETRI Journal
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• 제30권5호
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• pp.707-717
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• 2008

This paper presents two types of high-speed hardware architectures for the block cipher ARIA. First, the loop architectures for feedback modes are presented. Area-throughput trade-offs are evaluated depending on the S-box implementation by using look-up tables or combinational logic which involves composite field arithmetic. The sub-pipelined architectures for non-feedback modes are also described. With loop unrolling, inner and outer round pipelining techniques, and S-box implementation using composite field arithmetic over $GF(2^4)^2$, throughputs of 16 Gbps to 43 Gbps are achievable in a 0.25 ${\mu}m$ CMOS technology. This is the first sub-pipelined architecture of ARIA for high throughput to date.

• Journal of Power Electronics
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• 제10권3호
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• pp.228-234
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• 2010

This paper investigates the conducted-noise characteristics of a digitally-controlled randomly-switched dc-dc converter. In order to investigate the effect of the suggested digital controller on the conducted-noise characteristics of a dc-dc converter, three factors have been studied: the field-programmable gate array (FPGA) clock speed, the randomization ratio percentage, and the effect of using a closed loop feedback controller. A field-programmable gate array is much more flexible than analog control circuits, has a lower cost, and can be used for power supply applications. A novel FPGA-based implementation has been suggested for obtaining the experimental validations and realizing the studied concepts. Furthermore, the experimental results have been discussed and design guidelines have been included.

• 대한임베디드공학회논문지
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• 제14권6호
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• pp.313-319
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• 2019

Finite field operations have played an important role in error correcting codes and cryptosystems. Recently, the necessity of efficient computation processing is increasing for security in cyber physics systems. Therefore, efficient implementation of finite field arithmetics is more urgently needed. These operations include addition, multiplication, division and inversion. Addition is very simple and can be implemented with XOR operation. The others are somewhat more complicated than addition. Among these operations, multiplication is the most important, since time-consuming operations, such as exponentiation, division, and computing multiplicative inverse, can be performed through iterative multiplications. In this paper, we propose a multiplexer based parallel computation algorithm that performs Montgomery multiplication over finite field using redundant basis. Then we propose an efficient multiplexer based semi-systolic multiplier over finite field using redundant basis. The proposed multiplier has less area-time (AT) complexity than related multipliers. In detail, the AT complexity of the proposed multiplier is improved by approximately 19% and 65% compared to the multipliers of Kim-Han and Choi-Lee, respectively. Therefore, our multiplier is suitable for VLSI implementation and can be easily applied as the basic building block for various applications.

• Journal of Power Electronics
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• 제16권2호
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• pp.553-563
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• 2016

This paper presents a digital hardware implementation of a real-time simulator for a multiphase drive using a field-programmable gate array (FPGA) device. The simulator was developed with a modular and hierarchical design using very high-speed integrated circuit hardware description language (VHDL). Hence, this simulator is flexible and portable. A state-space representation model suitable for FPGA implementations was proposed for a dual three-phase induction machine (DTPIM). The simulator also models a two-level 12-pulse insulated-gate bipolar transistor (IGBT)-based voltage-source converter (VSC), a pulse-width modulation scheme, and a measurement system. Real-time simulation outputs (stator currents and rotor speed) were validated under steady-state and transient conditions using as reference an experimental test bench based on a DTPIM with 15 kW-rated power. The accuracy of the proposed digital hardware implementation was evaluated according to the simulation and experimental results. Finally, statistical performance parameters were provided to analyze the efficiency of the proposed DTPIM hardware implementation method.

• 한국경영과학회:학술대회논문집
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• 대한산업공학회/한국경영과학회 1994년도 춘계공동학술대회논문집; 창원대학교; 08월 09일 Apr. 1994
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• pp.627-632
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• 1994

This study suggests the contingency framework understanding the implementation of NIMT and conducts empirical analysis using survey data. The main objectives of the thesis are as follows : (1) analyzing the relationship between adaptation requirements and organizational adaptation efforts. (2) analyzing the relationship between organizational adaptation efforts and implementation performance, and the moderating effect of the adaptation requirements. (3) analyzing the relationship between organizational adaptation efforts and organization characteristics(organization size, technical capability, top management support). A field study was undertaken to test the hypothesized relationships among adaptation efforts, adaptations requirements, organization characteristics, implementation performance. Data were collected from 52 NMT implementation projects of 45 machine tool, metal component firms. The emprical relflts indicated that adaptation requirrnents, organization characteristics were significantly related to organizational adaptation efforts and adaptation efforts can significantly improve implementation perfomance, but the moderating effect of adaptation requirements on adaptation efforts and implementation performance was not supported.

• Journal of Power Electronics
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• 제10권3호
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• pp.300-305
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• 2010

This paper presents a two Hall sensor method for rotor angle detection in permanent magnet synchronous motors (PMSM). To minimize the implementation complexity, the system is designed to measure the edge field of permanent magnet pieces. However, there are nonlinearities in the measured values of the edge field. In this work, an angle correction algorithm is proposed, and the improvements in accuracy are verified through experiments. Finally, a field orientation controller is constructed with the proposed angle detection algorithm.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 신호처리소사이어티 추계학술대회 논문집
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• pp.115-118
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• 2003

In this paper we implemented a field-sequential stereoscopic endoscope system that can generate stereoscopic images with different perspective depth using LCD stutter. Re stereoscopic image is generated from stereoscopic adapter that has LCD shutter. We have compared the stereoscopic depth of a field-sequential stereoscopic endoscope system with that of the conventional endoscope system. And the implemented system is verified by evaluation the field-sequential stereoscopic image on a Monitor. This system will be use to medical instruments in time.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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• pp.183-192
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• 1999

The derivative equation measured of a MV=Kp8{(EVn-EVn-1)+Ki/S/1* EVn+(Kd/s)*(2PVn-1-{PVn-PVn-1)}(원문이미지참조) is used on the machine apparatus of industrial field, but this par doesn\`t able to educate now, because we didn\`t have the implementation device of PID module, so the principle implementation system of the PID Module is manufactured and developed. Through this system, the implementation system of PID Module is practiced with that the SV and the set of P, I, D is set on the derivative equation measured of PID. A things to be known of this experiment result is flow. 1)PID module is known that had to be used with the module of A/D and D/A. 2) In process of PV is approached to the SV to follow Kp, Ti and Td to cause a constant of set value on the MVp=Kp*EV, Mv=Ki/1 EVdt, MVd+tDBT/D EV(원문이미지참조) the variable rate of E and Kp, Td, Ti in that table 1 is analysed, is same as flow. ①If Kp is high, PV is near fast to the SV, but Kp is small, PV is near slowly to the SV. ②If Ki is shot, PV is close fast to the SV, but Ti is high, PV is close slowly to the SV ③If Td is high, the variable rate of E press hardly when because it doesn\`t increase, but Td is small, the variable rate of E press not hardly, upper with 1),2), PID module is supposed that be able to do the A/S and an implementation of that apparatus, and getting a success of aim that an engineer want, on control of temperature, tension, velocity, amount of flow, power of wind end so on, to get the principle of automatic implementation in industrial field with cooperation of A/D and D/A module.

• 대한전자공학회논문지SP
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• 제46권2호
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• pp.57-64
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• 2009

본 논문에서는 계층적 KLT 특징 추적기의 하드웨어 구조를 제안한다. 계층적 KLT 특징 추적기(pyramidal Kanade-Lucas-Tomasi feature tracker)는 주로 MPU를 기반으로 구현되어 왔으나 반복연산 과정이 많아 실시간으로 처리하기 어려우므로, 실시간 수행을 위하여 FPGA(Field Programmable Gate Array)를 이용하여 구현하였다. 본 논문에서는 추출되는 특징점의 수를 일정하게 유지하기 위해 입력 영상의 밝기에 적응적으로 임계값을 설정하는 특징점 추출 알고리즘을 제안한다. 또한 계층적 KLT 추적 알고리즘을 메모리의 용량 및 대역폭의 한계를 극복하고, FPGA의 병렬처리 특성에 적합한 구조로 변환한다. 소프트웨어로 실행한 결과와의 비교를 통하여 특징점의 추출 및 추적이 유사한 양상으로 이루어짐을 검증하였고, $720{\times}480$ 영상 입력에 대해 초당 30 프레임의 full frame rate로 추적이 수행됨을 확인하였다.