• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.171-172
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• 2007

We fabricated the metal-ferroelectric-insulator-semiconductor filed-effect transistors (MFIS-FETs) using the $(Bi,La)_4Ti_3O_{12}\;and\;LaZrO_x$ thin films. The $LaZrO_x$ thin film had a equivalent oxide thickness (EOT) value of 8.7 nm. From the capacitance-voltage (C-V) measurements for an Au/$(Bi,La)_4Ti_3O_{12}/LaZrO_x$/Si MFIS capacitor, a hysteric shift with a clockwise direction was observed and the memory window width was about 1.4 V for the bias voltage sweeping of ${\pm}9V$. From drain current-gate voltage $(I_D-V_G)$ characteristics of the fabricated Fe-FETs, the obtained threshold voltage shift (memory window) was about 1 V due to ferroelectric nature of BLT film. The drain current-drain voltage $(I_D-V_D)$ characteristics of the fabricated Fe-FETs showed typical n-channel FETs current-voltage characteristics.

• Korean Journal of Materials Research
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• v.10 no.4
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• pp.270-275
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• 2000

The Pt/YMnO$_3$/Y$_2$O$_3$/Si structure for metal/ferroelectric/insulator/semiconductor(MFIS)-FET was fabricated and effect of $Y_2$O$_3$layer on the properties of MFIS structure was investigated. The $Y_2$O$_3$ thin films on p-type Si(111) substrate deposited by Pulsed Laser Deposition were crystallized along (111) orientation irrespective of the deposition temperatures. Ferroelectric YMnO$_3$ thin films deposited directly on p-type Si (111) by MOCVD resulted in Mn deficient layer between Si and YMnO$_3$. However, YMnO$_3$ thin films having good quality and stoichiometric composition can be obtained by adopting $Y_2$O$_3$ buffer layer. The memory window of the $Y_2$O$_3$thin films with YMnO$_3$ film is greater than that of the YMnO$_3$ thin films without $Y_2$O$_3$ film after the annealing at 85$0^{\circ}C$ in vacuum ambient(100mtorr). The memory window is 1.3V at an applied voltage of 5V.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1130-1131
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• 2006

Here we report the effect of photo-spacer and polymer wall on the mechanical stability of the polymer-stabilized ferroelectric liquid crystal (PSFLC) system. A better bending tolerance of the PSFLC cell was obtained when the polymer wall was formed parallel to the rubbing direction. In addition, the effect of the distance between photo-spacer columns as well as that of the distance between polymer wall columns on the mechanical stability of the liquid crystal was examined.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.341-344
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• 2001

We investigate the electronic structure of perovskite PbTiO$_3$ and the microscopic origin of the ferroelectric lattice instability through first-principles pseudopotential calculations. We examine pseudo Jahn-Teller effect to discuss the lattice instability. The JT effect is caused by the hybridization of the p-orbitals of O atoms and d-orbital of Ti atom. We find the JT effect is most significant at Brillouin zone renter.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.3
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• pp.184-188
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• 2014

The electro-optic properties in Langmuir Blodgett films of poly (vinylidene fluoride trifluoroethylene) are investigated in the crossover region between two and three dimensions. The absence of finite size effect is observed in the films thinner than 20 nm, which confirms that these films are two dimensional ferroelectrics. The copolymer LB film of P(VDF-TrFE) exhibits the largest electro-optic response(26 pm/V) at 10 layer thickness. The cross-over behavior of electro-optic effect around the 10 layer thickness was discussed with the formation of nanomesa after thermal annealing.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.1
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• pp.88-92
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• 2023

The ferroelectricity in Hf_0.5Zr_0.5O₂ (HZO) thin films is one of the most interesting topics for next-generation nonvolatile memory applications. It is known that a crystallization process is required at a temperature of 400℃ or higher to form an orthorhombic phase that results in the ferroelectric properties of the HZO film. However, to realize the integration of ferroelectric HZO films in the back-end-of-line, it is necessary to reduce the annealing temperature below 400℃. This study aims to comprehensively analyze the ferroelectric properties according to the annealing temperature (350-500℃) and time (1-5 h) using a furnace as a crystallization method for HZO films. As a result, the ferroelectric behaviors of the HZO films were achieved at a temperature of 400℃ or higher regardless of the annealing time. At the annealing temperature of 350℃, the ferroelectric properties appeared only when the annealing time was sufficiently increased (4 h or more). Based on these results, it was experimentally confirmed that the optimization of the annealing temperature and time is very important for the ferroelectric phase crystallization of HZO films and the improvement of their ferroelectric properties.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.3
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• pp.190-194
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• 2003

Dielectric thin films of (P $b_{0.72}$,L $a_{0.28}$) $Ti_{0.93}$ $O_3$ (PLT(28)) have been deposited on Pt(111)/Ti/ $SiO_2$/Si(100) substrates in-situ by pulsed laser deposition using different annealing and deposition Processes. We have investigated the effect of hydrogen annealing on the ferroelectric properties of PLT thin films and found that the annealing process causes the diffusion of hydrogen into the ferroelectric film resulting in the destruction of polarization. We have tried to form the film by a two-step deposition process In order to improve electrical property. Two-step process to grow PLT films was adopted and verified to be useful to enlarge the grain size of the film and to reduce the leakage current characteristics. Structural properties and electrical properties including dielectric constant, ferroelectric characteristics, and leakage current of PLT thin films were shown to be strongly influenced by grain size. The film deposited by using two-step Process including pre-annealing treatment has a strongly(111) orientation. However, the films deposited by using single -step process with hydrogen annealing process show the smallest grain size. The film deposited by using two-step process including pre-annealing treatment shows the leakage current density of below 10$^{-7}$ A/c $m^2$ for the field of smaller than 100 kV/cm. However, the films deposited by using single-step process with hydrogen annealing process and pre-annealing process show worse leakage current density than the film deposited by using two-step process including pre-annealing treatment.tment.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.193-197
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• 2004

The effect of the temperature dependence of the smectic layer spacing in the smectic-A (SmA) phase on the formation of defects in the ferroelectric smectic-$C^{\ast}$ ($SmC^{\ast}$) phase is investigated with x-ray scattering technique. The study is based on thin parallel-aligned surface stabilized ferroelectric liquid crystal cells with two different alignment conditions, high pretilt $SiO_x$, alignment and low pretilt polyimide films. It is found that defects observed in the $SmC^{\ast}$ phase have much more profound dependence on the layer changes and chevron formation in the SmA phase than in the $SmC^{\ast}$ phase. We find that thermal layer expansion with decreasing temperature in the SmA phase suppresses the formation of defects observed in the SmC phase.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.55-58
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• 2000

This paper describes a single transistor type ferroelectric field effect transistor (1T FeFET) memory celt scheme which can select one unit memory cell and program/read it. To solve the selection problem of 1T FeEET memory cell array, the row direction common well is electrically isolated from different adjacent row direction column. So, we can control voltage of common well line. By applying bias voltage to Gate and Well, respectively, we can implant IT FeEET memory cell scheme which no interface problem and can bit operation. The results of HSPICE simulations showed the successful operations of the proposed cell scheme.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.403-405
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• 2000

This paper describes a single transistor type ferroelectric field effect transistor (1Tr FeFET) memory cell scheme, which select one unit memory cell and program/read it. The well voltage can be controlled by isolating the common row well lines. Through applying bias voltage to Gate and Well, respectively, we implement If FeFET memory cell scheme in which interference problem is not generated and the selection of each memory cell is possible. The results of HSPICE simulations showed the successful operations of the proposed cell scheme.