• The Pure and Applied Mathematics
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• v.26 no.2
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• pp.85-97
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• 2019

In this paper we introduce the reciprocal-negative Fermat's equation induced by the famous equation in the Fermat's Last Theorem, establish the general solution in the simplest cases and the differential solution to the equation, and investigate, then, the generalized Hyers-Ulam stability in a $quasi-{\beta}-normed$ space with both the direct estimation method and the fixed point approach.

• Communications of Mathematical Education
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• v.30 no.3
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• pp.335-351
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• 2016

The purpose of this study is to develop Project-Based Teaching-Learning materials for mathematically gifted students using a Fermat Point and apply the developed educational materials to practical classes, analyze, revise and correct them in order to make the materials be used in the field. I reached the conclusions as follows. First, Fermat Point is a good learning materials for mathematically gifted students. Second, when the students first meet the challenge of solving a problem, they observed, analyzed and speculated it with their prior knowledge. Third, students thought deductively and analogically in the process of drawing a conclusion based on observation. Fourth, students thought critically in the process of refuting the speculation. From the result of this study, the following suggestions can be supported. First, it is necessary to develop Teaching-Learning materials sustainedly for mathematically gifted students. Second, there needs a valuation criteria to analyze how learning materials were contributed to increase the mathematical ability. Third, there needs a follow up study about what characteristics of gifted students appeared.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.6
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• pp.1083-1091
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• 2017

This paper describes a design of cryptographic processor supporting 224-bit elliptic curves over prime field defined by NIST. Scalar point multiplication that is a core arithmetic function in elliptic curve cryptography(ECC) was implemented by adopting the modified Montgomery ladder algorithm. In order to eliminate division operations that have high computational complexity, projective coordinate was used to implement point addition and point doubling operations, which uses addition, subtraction, multiplication and squaring operations over GF(p). The final result of the scalar point multiplication is converted to affine coordinate and the inverse operation is implemented using Fermat's little theorem. The ECC processor was verified by FPGA implementation using Virtex5 device. The ECC processor synthesized using a 0.18 um CMOS cell library occupies 2.7-Kbit RAM and 27,739 gate equivalents (GEs), and the estimated maximum clock frequency is 71 MHz. One scalar point multiplication takes 1,326,985 clock cycles resulting in the computation time of 18.7 msec at the maximum clock frequency.

• Journal of KIISE:Computing Practices and Letters
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• v.7 no.6
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• pp.696-702
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• 2001

In this paper, we design IDEA cipher algorithm which is cryptographically superior to DES. To improve the encryption throughput, we propose an efficient design methodology for high-speed implementation of multiplicative inverse modulo $2^{15}$+1 which requires the most computing powers in IDEA. The efficient hardware architecture for the multiplicative inverse in derived from applying of Fermat's Theorem. The computing powers for multiplicative inverse in our proposal is a decrease 50% compared with the existing method based on Extended Euclid Algorithm. We implement IDEA by applying a single iterative round method and our proposal for multiplicative inverse. With a system clock frequency 20MGz, the designed hardware permits a data conversion rate of more than 116 Mbit/s. This result show that the designed device operates about 2 times than the result of the paper by H. Bonnenberg et al. From a speed point of view, out proposal for multiplicative inverse is proved to be efficient.

• Journal of Information Processing Systems
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• v.13 no.4
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• pp.677-688
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• 2017

In order to solve the undetected probability of multiple targets in ultra-wideband (UWB) through-the-wall radar imaging (TWRI), a time-delay and amplitude modified back projection (BP) algorithm is proposed. The refraction point is found by Fermat's principle in the presence of a wall, and the time-delay is correctly compensated. On this basis, transmission loss of the electromagnetic wave, the absorption loss of the refraction wave, and the diffusion loss of the spherical wave are analyzed in detail. Amplitude compensation is deduced and tested on a model with a single-layer wall. The simulating results by finite difference time domain (FDTD) show that it is effective in increasing the scattering intensity of the targets behind the wall. Compensation for the diffusion loss in the spherical wave also plays a main role. Additionally, the two-layer wall model is simulated. Then, the calculating time and the imaging quality are compared between a single-layer wall model and a two-layer wall model. The results illustrate the performance of the time-delay and amplitude-modified BP algorithm with multiple targets and multiple-layer walls of UWB TWRI.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.12
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• pp.1609-1617
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• 2019

Described in this paper is a design of hardware accelerator for implementing public-key cryptographic protocols (PKCPs) based on Elliptic Curve Cryptography (ECC) and RSA. It supports five elliptic curves (ECs) over GF(p) and three key lengths of RSA that are defined by NIST standard. It was designed to support four point operations over ECs and six modular arithmetic operations, making it suitable for hardware implementation of ECC- and RSA-based PKCPs. In order to achieve small-area implementation, a finite field arithmetic circuit was designed with 32-bit data-path, and it adopted word-based Montgomery multiplication algorithm, the Jacobian coordinate system for EC point operations, and the Fermat's little theorem for modular multiplicative inverse. The hardware operation was verified with FPGA device by implementing EC-DH key exchange protocol and RSA operations. It occupied 20,800 gate equivalents and 28 kbits of RAM at 50 MHz clock frequency with 180-nm CMOS cell library, and 1,503 slices and 2 BRAMs in Virtex-5 FPGA device.