• Journal of the Korea Institute of Information Security & Cryptology
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• v.27 no.3
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• pp.467-476
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• 2017

In this paper, we analyze Generalized Feistel Network(GFN) Type I, Type II, Type III that round function use SP update function, secret S-box and $k{\times}k$ MDS matirx. In this case an attacker has no advantage about S-box. For each type of GFN, we analyze and restore secret S-box in 9, 6, 6 round using the basis of integral cryptanalysis with chosen plaintext attack. Also we restore secret S-box in 16 round of GFN Type I with chosen ciphertext attack. In conclusion, we need $2^{2m}$ data complexity and ${\frac{2^{3m}}{32k}},{\frac{2^{3m}}{24k}},{\frac{2^{3m}}{36k}}$ time complexity to restore m bit secret S-box in GFN Type I, Type II, Type III.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.404-406
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• 2015

This paper describes a small-area hardware implementation of the block cipher algorithm CLEFIA-128 which supports for 128-bit master key. A compact structure using single data processing block is adopted, which shares hardware resources for round transformation and the generation of intermediate values for round key scheduling. In addition, data processing and key scheduling blocks are simplified by utilizing a modified GFN(generalized Feistel network) and key scheduling scheme. The CLEFIA-128 crypto-processor is verified by FPGA implementation. It consumes 823 slices of Virtex5 XC5VSX50T device and the estimated throughput is about 105 Mbps with 145 MHz clock frequency.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1997.11a
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• pp.303-314
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• 1997

계산능력이 제한된 8비트 마이크로프로세서에 적합하도록 모든 기본 연산을 8비트 단위로 처리하는, 블록 크기는 64비트, 키 크기는 128비트인, Feistel 구조의 블록 암호 알고리즘을 제시한다. 이 알고리즘의 안전도는 잘 알려진 two-key triple-DES[ANSI86]나 IDEA[Lai92]와 비견할 만하며, 처리속도는 single-DES[NBS77]보다도 10∼20배 빠르다. 본 논문에서는 이 알고리즘의 설계원칙 및 안전성 분석에 대하여 설명하였고, 다른 알고리즘과의 통계적 특성 및 성능에 대해서도 비교하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.10b
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• pp.823-830
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• 2001

본 논문에서는 데이터 의존 회전 기법과 프로그램 셀룰라 오토마타 기법을 사용한 블록 암호 알고리즘인 가칭 Pkc128(PuKyong Code 128) 암호 알고리즘을 제안한다. 제안한 암호 알고리즘의 블록 크기는 128 비트이고, 키의 치기는 128 비트 이상 가변이며 Feistel Network 구조를 취하였다. 제안한 알고리즘의 안전성을 검정하기 위하여 출력 스트림에 대한 통계적 검정을 실시하였다. 그 결과 16 회전 시에 모든 검정과정을 통과하여 제안된 알고리즘이 통계적으로 안전함을 확인하였다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.30 no.5
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• pp.795-803
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• 2020

In this paper, we study known-key distinguishing and partial-collision attacks on GFN-2 structures with SP F-functions and various block lengths. Firstly, we show the known-key distinguishing attack is possible up to 15 rounds. Secondly, for the case that the last round function has the shuffle operation, we show that the partial-collision attack is possible up to 14 rounds. Finally, for the case that the last round function has no shuffle operation, we show that the partial-collision attacks are possible up to 11 rounds.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.8-15
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• 2007

This paper proposed hardware architecture of the block cryptographic algorithm HIGHT aiming small size and low power application, and analyzed its performance. The HIGHT is a modified algorithm of the Feistel. The encryption and decryption circuit were designed as one iterative block. It reduces the redundant circuit that yields small area. For the performance improvement, the circuit generates 32-bit subkey during 1 clock cycle. we synthesized the HIGHT with Hynix $0.25-{\mu}m$ CMOS technology. The proposed circuit size was 2.658 EG(equivalent gate), and its power consumption was $10.88{\mu}W$ at 2.5V for 100kHz. It is useful for a passive RFID tag or a smart IC card of a small size and low power.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.12
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• pp.974-980
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• 2000

Luby-Rackoff의 논문 이후로 유사 랜덤 순열 생성기에 관한 많은 연구가 있었다. 하지만 대부분의 연구는 대칭 피스텔 네트웍 구조를 이용한 유사 랜덤 순열 생성기에 관한 것이었다. 이 논문에서는 비대칭 피스텔 네트웍 구조를 사용하는 순열 생성기가 유사 랜덤 순열 생성기가 되기 위한 조건을 분석한다. 비대칭 피스텔 네트웍 순열 생성기의 입출력의 크기가 (k+1)n 비트인 경우 논문의 결과는 다음과 같다. 비대칭 피스텔 네트웍이 입력 크기가 kn 비트이고 출력 크기가 n 비트인 유사 랜덤 함수 생성기를 사용하는 경우, 전체 라운드 수가 k+2 이상이면 유사 랜덤 순열 생성기이다. 비대칭 피스텔 네트웍이 입력 크기가 n 비트이고 출력 크기가 kn 비트인 유사 랜덤 함수 생성기를 사용하는 경우, 전체 라운드 수가 k+2 이상이면 유사 랜덤 순열 생성기이다.

• Journal of the Korea Society of Computer and Information
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• v.17 no.1
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• pp.171-181
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• 2012

This paper defines the AES password algorithm used as a symmetric-key-based password algorithm, and proposes the design of parallel password algorithm to utilize the resources of multi-core processor as much as possible. The proposed parallel password algorithm was confirmed for parallel execution of password computation by allocating the password algorithm according to the number of cores, and about 30% of performance increase compared to AES password algorithm. The encryption/decryption performance of the password algorithm was confirmed through binary comparative analysis tool, which confirmed that the binary results were the same for AES password algorithm and proposed parallel password algorithm, and the decrypted binary were also the same. The parallel password algorithm for multi-core environment proposed in this paper can be applied to authentication/payment of financial service in PC, laptop, server, and mobile environment, and can be utilized in the area that required high-speed encryption operation of large-sized data.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.351-358
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• 2016

This paper describes an efficient hardware implementation of lightweight block cipher algorithm CLEFIA. The CLEFIA crypto-processor supports for three master key lengths of 128/192/256-bit, and it is based on the modified generalized Feistel network (GFN). To minimize hardware complexity, a unified processing unit with 8 bits data-path is designed for implementing GFN that computes intermediate keys to be used in round key scheduling, as well as carries out round transformation. The GFN block in our design is reconfigured not only for performing 4-branch GFN used for round transformation and intermediate round key generation of 128-bit, but also for performing 8-branch GFN used for intermediate round key generation of 256-bit. The CLEFIA crypto-processor designed in Verilog HDL was verified by using Virtex5 XC5VSX50T FPGA device. The estimated throughput is 81.5 ~ 60 Mbps with 112 MHz clock frequency.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.1
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• pp.121-125
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• 2007

Differential cryptanalysis and linear cryptanalysis are the most powerful approaches known for attacking many block ciphers and used to evaluating the security of many block ciphers. So designers have designed secure block ciphers against these cryptanalyses. In this paper, we present new three block cipher structures. And for given r, we prove that differential(linear) probabilities for r-round blockcipher structures are upper bounded by $p^2(q^2),\;2p^2(2q^2)$ if the maximum differential(linear) probability is p(q) and the round function is a bijective function.