• Title/Summary/Keyword: FeFET

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Current Status and Prospects of FET-type Ferroelectric Memories

  • Ishiwara, Hiroshi
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.1 no.1
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    • pp.1-14
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    • 2001
  • Current status and prospects of FET-type FeRAMs (ferroelectric random access memories) are reviewed. First, it is described that the most important issue for realizing FET-type FeRAMs is to improve the data retention characteristics of ferroelectric-gate FETs. Then, necessary conditions to prolong the retention time are discussed from viewpoints of materials, device structure, and circuit configuration. Finally, recent experimental results related to the FET-type memories are introduced, which include optimization of a buffer layer that is inserted between the ferroelectric film and a Si substrate, development of a new ferroelectric film with a small remnant polarization value, proposal and fabrication of a 1T2C-type memory cell with good retention characteristics, and so on.

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Sense Amplifier Design for A NOR Type Non-Volatile Memory

  • Yang, Yil-Suk;Yu, Byoung-Gon;Roh, Tae-Moon;Koo, Jin-Gun;Kim, Jongdae
    • Proceedings of the IEEK Conference
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    • 2002.07c
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    • pp.1555-1557
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    • 2002
  • We have investigated the precharge type sense amplifier, it is suitable fur voltage sensing in a NOR type single transistor ferroelectric field effect transistor (1T FeFET) memory read operation. The proposed precharge type sense amplifier senses the bit line voltage of 1T FeFET memory. Therefore, the reference celt is not necessary compared to current sensing in 1T FeFET memory, The high noise margin is wider than the low noise margin in the first inverter because requires tile output of precharge type sense amplifier high sensitivity to transition of input signal. The precharge type sense amplifier has very simple structure and can sense the bit line signal of the 1T FeFET memory cell at low voltage.

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Fabrication and Characterization of MFIS-FET using Au/SBT/LZO/Si structure

  • Im, Jong-Hyun;Lee, Gwang-Geun;Kang, Hang-Sik;Jeon, Ho-Seung;Park, Byung-Eun;Kim, Chul-Ju
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.06a
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    • pp.174-174
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    • 2008
  • Non-volatile memories using ferroelectric-gate field-effect transistors (Fe-FETs) with a metal/ferroelectric/semiconductor gate stack (MFS-FETs) make non-destructive read operation possible. In addition, they also have features such as high switching speed, non-volatility, radiation tolerance, and high density. However, the interface reaction between ferroelectric materials and Si substrates, i.e. generation of mobile ions and short retention, make it difficult to obtain a good ferroelectric/Si interface in an MFS-FET's gate. To overcome these difficulties, Fe-FETs with a metal/ferroelectric/insulator/semiconductor gate stack (MFIS-FETs) have been proposed, where insulator as a buffer layer is inserted between ferroelectric materials and Si substrates. We prepared $SrBi_2Ta_2O_9$ (SBT) film as a ferroelectric layer and $LaZrO_x$ (LZO) film as a buffer layer on p-type (100) silicon wafer for making the MFIS-FET devices. For definition of source and drain region, phosphosilicate glass (PSG) thin film was used as a doping source of phosphorus (P). Ultimately, the n-channel ferroelectric-gate FET using the SBT/LZO/Si Structure is fabricated. To examine the ferroelectric effect of the fabricated Fe-FETs, drain current ($I_d$) versus gate voltage ($V_g$) characteristics in logarithmic scale was measured. Also, drain current ($I_d$) versus drain voltage ($V_d$) characteristics of the fabricated SBT/LZO/Si MFIS-FETs was measured according to the gate voltage variation.

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A Study on the Reduction of Iron Oxide from Slag in the EAF Process (전기로 공정에서 슬래그 중 산화철의 환원 회수에 관한 연구)

  • Kim, Young-Hwan;Yoo, Jung-Min
    • Resources Recycling
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    • v.25 no.4
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    • pp.54-59
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    • 2016
  • EAF processed slag which contains about 20 ~ 35 weight percent FetO is poured to slag pot and cooled. If we recover Fe from molten slag by the reduction, we will improve steel yield rate and reduce slag quantity poured from the furnace. Usually, carbon is used as a reductant and slag foaming agent in the EAF process. In this experiment, after melt the metal in induction furnace and then add slag with carbon and Al dross powder as a reductant, we investigated the reduction of FetO from slag and change of Phophorus content. As the result, when we use Al dross as a reductant, recovery rate is two times more than carbon. Phosphorus pick up is less than 50ppm with reduction of EAF slag.

Recent Development in Polymer Ferroelectric Field Effect Transistor Memory

  • Park, Youn-Jung;Jeong, Hee-June;Chang, Ji-Youn;Kang, Seok-Ju;Park, Cheol-Min
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.1
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    • pp.51-65
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    • 2008
  • The article presents the recent research development in polymer ferroelectric non-volatile memory. A brief overview is given of the history of ferroelectric memory and device architectures based on inorganic ferroelectric materials. Particular emphasis is made on device elements such as metal/ferroelectric/metal type capacitor, metal-ferroelectric-insulator-semiconductor (MFIS) and ferroelectric field effect transistor (FeFET) with ferroelectric poly(vinylidene fluoride) (PVDF) and its copolymers with trifluoroethylene (TrFE). In addition, various material and process issues for realization of polymer ferroelectric non-volatile memory are discussed, including the control of crystal polymorphs, film thickness, crystallization and crystal orientation and the unconventional patterning techniques.

Fabrication and Estimation of Single-Transistor-Cell-Type FeRAM (MFS-FET) Using SOI Substrate (SOI 기판을 이용한 1-트랜지스터 구조 강유전체 비휘발성 메모리(MFS-FET)의 제작 및 평가)

  • Kim, N.K.;Lee, S.J.;Choi, H.B.;Kim, C.J.
    • Proceedings of the KIEE Conference
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    • 1999.11d
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    • pp.921-923
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    • 1999
  • 비휘발성 메모리의 고집적화와 적응학습형 뉴럴 소자의 실현을 위하여 1-트랜지스터 구조 강유전체 비휘발성 메모리(MFS-FET)를 SOI 기판위에 제작하고 평가하였다. 먼저 SBT($Sr_{0.8}Bi_{2.2}Ta_{2}O_{9}$)를 직접 Si위에 증착하고 C-V를 측정하여 1V의 메모리 윈도우를 얻음으로써 비휘발성 메모리로써의 동작가능성을 확인하였다. 또한 다양하게 게이트의 W/L 비를 바꾸어서 MFS-FET를 제작하여 다양한 드레인 전압-드레인 전류 특성을 얻었고 실제로 쓰기와 읽기 동작을 수행하여 MFS-FET가 비휘발성 메모리로써 제대로 동작하고 있음을 확인하였다.

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Enhanced pH Response of Solution-gated Graphene FET by Using Vertically Grown ZnO Nanorods on Graphene Channel

  • Kim, B.Y;Jang, M.;Shin, K.-S.;Sohn, I.Y;Kim, S.-W.;Lee, N.-E
    • Proceedings of the Korean Vacuum Society Conference
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    • 2014.02a
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    • pp.434.2-434.2
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    • 2014
  • We observe enhanced pH response of solution-gated field-effect transistors (SG-FET) having 1D-2D hybrid channel of vertical grown ZnO nanorods grown on CVD graphene (Gr). In recent years, SG-FET based on Gr has received a lot of attention for biochemical sensing applications, because Gr has outstanding properties such as high sensitivity, low detection limit, label-free electrical detection, and so on. However, low-defect CVD Gr has hardly pH responsive due to lack of hydroxyl group on Gr surface. On the other hand, ZnO, consists of stable wurtzite structure, has attracted much interest due to its unique properties and wide range of applications in optoelectronics, biosensors, medical sciences, etc. Especially, ZnO were easily grown as vertical nanorods by hydrothermal method and ZnO nanostructures have higher sensitivity to environments than planar structures due to plentiful hydroxyl group on their surface. We prepared for ZnO nanorods vertically grown on CVD Gr (ZnO nanorods/Gr hybrid channel) and to fabricate SG-FET subsequently. We have analyzed hybrid channel FETs showing transfer characteristics similar to that of pristine Gr FETs and charge neutrality point (CNP) shifts along proton concentration in solution, which can determine pH level of solution. Hybrid channel SG-FET sensors led to increase in pH sensitivity up to 500%, compared to pristine Gr SG-FET sensors. We confirmed plentiful hydroxyl groups on ZnO nanorod surface interact with protons in solution, which causes shifts of CNP. The morphology and electrical characteristics of hybrid channel SG-FET were characterized by FE-SEM and semiconductor parameter analyzer, respectively. Sensitivity and sensing mechanism of ZnO nanorods/Gr hybrid channel FET will be discussed in detail.

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A Nonvolatile Refresh Scheme Adopted 1T-FeRAM for Alternative 1T-DRAM

  • Kang, Hee-Bok;Choi, Bok-Gil;Sung, Man-Young
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.1
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    • pp.98-103
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    • 2008
  • 1T1C DRAM has been facing technological and physical constraints that make more difficult their further scaling. Thus there are much industrial interests for alternative technologies that exploit new devices and concepts to go beyond the 1T1C DRAM technology, to allow better scaling, and to enlarge the memory performance. The technologies of DRAM cell are changing from 1T1C cell type to capacitor-less 1T-gain cell type for more scalable cell size. But floating body cell (FBC) of 1T-gain DRAM has weak retention properties than 1T1C DRAM. FET-type 1T-FeRAM is not adequate for long term nonvolatile applications, but could be a good alternative for the short term retention applications of DRAM. The proposed nonvolatile refresh scheme is based on utilizing the short nonvolatile retention properties of 1T-FeRAM in both after power-off and power-on operation condition.

A study for use a vanadium oxide in steel manufacture (제강 공정중 산화바나듐활용 연구)

  • Choi, Young-Key
    • Journal of environmental and Sanitary engineering
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    • v.24 no.3
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    • pp.55-61
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    • 2009
  • Fe-V is used as raw material of vanadium in the steel making process. The purpose of this study, Fe-V is to replace the $VO_{4}$. So the distribution behavior of vanadium in $VO_{4}$ of the steel investigated. The distribution ratio of the vanadium where potential of the free oxygen ion will increase in slag decreased. When CaO and MgO content which is a basic oxide from CaO-$SiO_2$-FetO-MgOsatd. slag increases, S distribution ratio increases. CaO-$SiO_2$-FetO-MgOsatd. slag better than CaO-$SiO_2$-$Al_2O_3$-MgO slag is the recovery of vanadum and desulfurization.

A Single Transistor Type Ferroelectric Field-Effect-Transistor Cell Scheme

  • Yang, Yil-Suk;You, In-Kyu;Lee, Wong-Jae;Yu, Byoung-Gon;Cho, Kyong-Ik
    • Proceedings of the IEEK Conference
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    • 2000.07a
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    • pp.403-405
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    • 2000
  • This paper describes a single transistor type ferroelectric field effect transistor (1Tr FeFET) memory cell scheme, which select one unit memory cell and program/read it. The well voltage can be controlled by isolating the common row well lines. Through applying bias voltage to Gate and Well, respectively, we implement If FeFET memory cell scheme in which interference problem is not generated and the selection of each memory cell is possible. The results of HSPICE simulations showed the successful operations of the proposed cell scheme.

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