• The Journal of the Korea institute of electronic communication sciences
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• v.5 no.4
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• pp.443-449
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• 2010

Current testing is an effective method which offers higher fault detection and diagnosis capabilities than voltage testing. Since current testing requires much longer testing time than voltage testing, it is important to note that a fault is untestable if the two nodes have same values at all times. In this paper, we present an object oriented fault detection scheme for various fault models using current testing. Experimental results for ISCAS benchmark circuits show the effectiveness of the proposed method in reducing the number of faults and its usefulness in various fault models.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.63-71
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• 2003

IDDQ testing is indispensable in improving Duality and reliability of CMOS VLSI circuits. But the major problem of IDDQ testing is slow testing speed due to time-consuming IDDQ current measurement. So one requirement is to reduce the number of target faults or to make the test sets compact in fault model. In this paper, we consider equivalent fault collapsing for transistor short faults, a fault model often used in IDDQ testing and propose an efficient algorithm for reducing the number of faults that need to be considered by equivalent fault collapsing. Experimental results for ISCAS benchmark circuits show the effectiveness of the proposed method.

• Electrical & Electronic Materials
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• v.10 no.4
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• pp.349-354
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• 1997

This paper aims at studying the improvement of test method for t-weight sensitive fault (t-wsf) detect. The development of RAM fabrication technology results in not only the increase at device density on chips but also the decrease in line widths in VLSI. But, the chip size that was large and complex is shortened and simplified while the cost of chips remains at the present level, in many cases, even lowering. First of all, The testing patterns for RAM fault detect, which is apt to be complicated , need to be simplified. This new testing method made use of Local Lower Bound (L.L.B) which has the memory with the beginning pattern of 0(l) and the finishing pattern of 0(1). The proposed testing patterns can detect all of RAM faults which contain stuck-at faults, coupling faults. The number of operation is 6N at 1-weight sensitive fault, 9,5N at 2-weight sensitive fault, 7N at 3-weight sensitive fault, and 3N at 4-weight sensitive fault. This test techniques can reduce the number of test pattern in memory cells, saving much more time in test, This testing patterns can detect all static weight sensitive faults and pattern sensitive faults in RAM.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.176-186
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• 1996

As the density of VLSI increases, the conventional logic testing is not sufficient to completely detect the new faults generated in design and fabrication processing. Recently, IDDQ testing becomes very attractive since it can overcome the limitations of logic testing. In this paper, G-ATPG (gyeongsang automatic test pattern genrator) is designed which is able to be adapted to IDDQ testing for combinational CMOS VLSI. In G-ATPG, stuck-at, transistor stuck-on, GOS (gate oxide short)or bridging faults which can occur within priitive gate or XOR is modelled to primitive fault patterns and the concept of a fault-sensitizing gate is used to simulate only gates that need to sensitize the faulty gate because IDDQ test does not require the process of fault propagation. Primitive fault patterns are graded to reduce CPU time for the gates in a circuit whenever a test pattern is generated. the simulation results in bench mark circuits show that CPU time and fault coverage are enhanced more than the conventional ATPG using IDDQ test.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1C
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• pp.96-102
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• 2002

Current testing(Iddq testing) on monitoring the quiescent power supply current is an efficient and effective method for CMOS bridging faults. The applicability of this technique, however, requires careful examination. Since cardinality of bridging fault is O($n^2$) and current testing requires much longer testing time than voltage testing, it is important to note that a bridging fault is untestable if the two bridged nodes have the same logic values at all times. Such faults should be identified by a good ATPG tool; otherwise, the fault coverage can become skewed. In this paper, we present an object-oriented redundant fault detection scheme for efficient current testing. Experimental results for ISCAS benchmark circuits show that the improved method is more effective than the previous ones.

• Proceedings of the KIEE Conference
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• 1999.07c
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• pp.1126-1129
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• 1999

In this paper theoretical review for the design and the algorithm of Artificial Fault Generator, on the power distribution center is which able to purposely generate and get rid of fault with the view of testing distribution systems including switchgears, was made. For the following paper verification with EMTP will be performed in order to review the function and the algorithm so that the optimized design can be established.

• Proceedings of the KSR Conference
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• 1998.05a
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• pp.408-418
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• 1998

This paper presents the implementation of comparator which is self-testing with respect to the faults caused by any single physical defect likely to occur in NMOS and CMOS integrated circuit. The goal is to use it for the fault-tolerant system. First, a new fault model for PLA(Programmable Logic Array) is presented. This model reflects several physical defects in VLSI circuits. It focuses on the designs based on PLA because VLSI chips are far too complex to allow detailed analysis of all the possible physical defects that can occur and of the effects on the operation of the circuit. Second, this paper shows that these design, which has been implemented with 2 level AND-ORor NOR-NOR circuit, are optimal in term of size. And it also presents a formal proof that a comparator implemented using NOR-NOR PLA, based on these design, is sol f-testing with respect to most single faults in the presented fault model. Finally, it discusses the application of the self-testing comparator as a building block for the implementation of the fault-tolerant system.

• International Journal of Reliability and Applications
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• v.8 no.1
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• pp.53-66
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• 2007

This paper proposes a new non-homogeneous Poisson process software reliability growth model based on the coverage information. The new model incorporates the coverage information in the fault detection process by assuming that only the faults in the covered constructs are detectable. Since the coverage growth behavior depends on the testing strategy, the fault detection process is first modeled for the general testing strategy and then realized for the uniform testing. Finally the model for the uniform testing is empirically evaluated by applying it to real data sets.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.7
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• pp.1394-1402
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• 1997

In this work, an efficient test algorithm and BIST architeture a for embedded memories are presented. The proposed test algorithm can fully detect stuck-at fault, transition fault, coupling fault. Moreover, the proposed test algorithm can detect nighborhood pattern sensitive fault which could not be detected in previous march test algoarithms. The proposed test algorithm perposed test algorithm performs testing for neghborhood pattern sensitive fault using backgroung data which has been used word-oriented memory testing.

• Journal of Advanced Navigation Technology
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• v.14 no.1
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• pp.119-126
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• 2010

The software reliability growth model(SRGM) has been developed in order to estimate such reliability measures as remaining fault number, failure rate and reliability for the developing stage software. Almost of them assumed that the faults detected during testing were eventually removed. Namely, they have studied SRGM based on the assumption that the faults detected during testing were perfectly removed. The fault removing efficiency, however, is imperfect and it is widely known as so in general. It is very difficult to remove detected fault perfectly because the fault detecting is not easy and new error may be introduced during debugging and correcting. Therefore, We want to study imperfect software testing effort for the logistic testing effort which is thought to be the most adequate in this paper.