• Proceedings of the KSR Conference
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• 2000.05a
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• pp.330-335
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• 2000

Faults detection and containment requirements are typically allocated from a top-level specification as a percentage of total faults detection and containment, weighted by failure rate. This faults detection and containments are called as a fault coverage. The fault coverage requirements are typically allocated identically to all units in the system, without regard to complexity, cost of implementation or failure rate for each units. In this paper a simple methodology and mathematical model to support the allocation of system fault coverage rates to lower-level units by considering the inherent differences in reliability is presented. The models are formed as a form of constrained optimization. The objectives and constraints are modeled as a linear form and this problems are solved by linear programming. It is identified by simulation that the proposed solving methods for these problems are effective to such requirement allocating.

• Nuclear Engineering and Technology
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• v.44 no.4
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• pp.421-428
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• 2012

Analog instrument and control systems in nuclear power plants have recently been replaced with digital systems for safer and more efficient operation. Digital instrument and control systems have adopted various fault-tolerant techniques that help the system correctly and safely perform the specific required functions regardless of the presence of faults. Each fault-tolerant technique has a different inspection period, from real-time monitoring to monthly testing. The range covered by each faulttolerant technique is also different. The digital instrument and control system, therefore, adopts multiple barriers consisting of various fault-tolerant techniques to increase the total fault detection coverage. Even though these fault-tolerant techniques are adopted to ensure and improve the safety of a system, their effects on the system safety have not yet been properly considered in most probabilistic safety analysis models. Therefore, it is necessary to develop an evaluation method that can describe these features of digital instrument and control systems. Several issues must be considered in the fault coverage estimation of a digital instrument and control system, and two of these are addressed in this work. The first is to quantify the fault coverage of each fault-tolerant technique implemented in the system, and the second is to exclude the duplicated effect of fault-tolerant techniques implemented simultaneously at each level of the system's hierarchy, as a fault occurring in a system might be detected by one or more fault-tolerant techniques. For this work, a fault injection experiment was used to obtain the exact relations between faults and multiple barriers of faulttolerant techniques. This experiment was applied to a bistable processor of a reactor protection system.

• International Journal of Reliability and Applications
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• v.8 no.1
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• pp.53-66
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• 2007

This paper proposes a new non-homogeneous Poisson process software reliability growth model based on the coverage information. The new model incorporates the coverage information in the fault detection process by assuming that only the faults in the covered constructs are detectable. Since the coverage growth behavior depends on the testing strategy, the fault detection process is first modeled for the general testing strategy and then realized for the uniform testing. Finally the model for the uniform testing is empirically evaluated by applying it to real data sets.

• Nuclear Engineering and Technology
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• v.51 no.3
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• pp.692-701
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• 2019

Recently, instrumentation and control (I&C) systems in nuclear power plants have undergone digitalization. Owing to the unique characteristics of digital I&C systems, the reliability analysis of digital systems has become an important element of probabilistic safety assessment (PSA). In a reliability analysis of digital systems, fault-tolerant techniques and their effectiveness must be considered. A fault injection experiment was performed on a safety-critical digital I&C system developed for nuclear power plants to evaluate the effectiveness of fault-tolerant techniques implemented in the target system. A software-implemented fault injection in which faults were injected into the memory area was used based on the assumption that all faults in the target system will be reflected in the faults in the memory. To reduce the number of required fault injection experiments, the memory assigned to the target software was analyzed. In addition, to observe the effect of the fault detection coverage of fault-tolerant techniques, a PSA model was developed. The analysis of the experimental result also can be used to identify weak points of fault-tolerant techniques for capability improvement of fault-tolerant techniques

• Proceedings of the KSR Conference
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• 1998.11a
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• pp.270-279
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• 1998

This paper presents the design of self-checking comparator using the time diversity and the application to 8 bit CPU for the implementation of fault tolerant computer system. this self-checking comparator was designed with the different time Points in which temporary faults were raised by electrical noise between duplicated functional blocks. also this self-checking comparator was simulated in the method of the fault injection using 4 bit shift register counter. we designed the duplicated Emotional block and the self-checking comparator in the single chip using the Altera EPLD and could verify the reliability and the fault detection coverage through the modeling of temporary faults ,especially intermittent faults. at the results of this research, the reliability and the fault detection coverage were implemented through the self-checking comparator using the time diversity.

• The KIPS Transactions:PartD
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• v.11D no.6
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• pp.1287-1294
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• 2004

Recently relationships between reliability measures and the coverage have been developed for evaluation of software reliability. Particularly the mean value function of the coverage-based software reliability growth model is important because of its key role in rep-resenting the software reliability growth. In this paper, we first review the problems of the existing mean value functions with respect to the assumptions on which they are based. Then a new mean value function is proposed. The new mean value function is developed for a general testing environment in which imperfect fault detection and repeated construct execution are allowed. Finally performance of the proposed model is empirically evaluated by applying it to a real data set.

• International Journal of Reliability and Applications
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• v.7 no.2
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• pp.155-166
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• 2006

Many software reliability growth models (SRGMs) based on nonhomogeneous Poisson process (NHPP) have been developed and applied in practice. NHPP SRGMs are characterized by their mean value functions. Mean value functions are usually derived from differential equations representing the fault detection/removal process during testing. In this paper such differential equations are regarded as frameworks for generating mean value functions. Currently available frameworks are theoretically discussed with respect to capability of representing the fault detection/removal process. Then two general frameworks are proposed.

• ETRI Journal
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• v.31 no.2
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• pp.209-214
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• 2009

In this paper, we propose a novel test methodology for the detection of catastrophic and parametric faults present in analog very large scale integration circuits. An automatic test pattern generation algorithm is proposed to generate piece-wise linear (PWL) stimulus using wavelets and a genetic algorithm. The PWL stimulus generated by the test algorithm is used as a test stimulus to the circuit under test. Faults are injected to the circuit under test and the wavelet coefficients obtained from the output response of the circuit. These coefficients are used to train the neural network for fault detection. The proposed method is validated with two IEEE benchmark circuits, namely, an operational amplifier and a state variable filter. This method gives 100% fault coverage for both catastrophic and parametric faults in these circuits.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.7
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• pp.994-1002
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• 2013

This study suggests a generalized availability and safety evaluation model to evaluate the influences to the system's fault tolerant capabilities depending on automatic fault detection function such as the automatic periodic testings. The conventional evaluation model of automatic fault detection function deals only with the self diagnostics, and supposes that the fault detection coverage of self diagnostics is always constant. But all of the fault detection methods could be degraded. For example, the periodic surveillance test has the potential human errors or test equipment errors, the self diagnostics has the potential degradation of built-in logics, and the automatic periodic testing has the potential degradation of automatic test facilities. The suggested evaluation models have incorporated the loss or erroneous behaviors of the automatic fault detection methods. The availability and the safety of each module of the safety grade platform have been evaluated as they were applied the automatic periodic test methodology and the fault tolerant evaluation models. The availability and safety of the safety grade platform were improved when applied the automatic periodic testing. Especially the fault tolerant capability of the processor module with a weak self-diagnostics and the process parameter input modules were dramatically improved compared to the conventional cases. In addition, as a result of the safety evaluation of the digital reactor protection system, the system safety of the digital parts was improved about 4 times compared to the conventional cases.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.14-24
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• 2009

Memory cell array and peripheral circuits are designed for system on panel style frame buffer. Moreover, a parallel test methodology to test multiple blocks of memory cells is proposed to overcome low yield of system on panel processing technologies. It is capable of faster fault detection compared to conventional memory tests and also applicable to the tests of various embedded memories and conventional SRAMs. The various patterns of conventional test vectors can be used to enhance fault coverage. The proposed testing method is also applicable to hierarchical bit line and divided word line, one of design trends of recent memory architectures.