• Nuclear Engineering and Technology
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• v.41 no.1
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• pp.91-98
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• 2009

The "3+3 Process" for safety critical software for nuclear power plants' I&C (Instrumentation and Control system) has been developed in this work. The main idea of the "3+3 Process" is both to simplify the software development and safety analysis in three steps to fulfill the requirements of a software safety plan [1]. The "3-Step" software development process consists of formal modeling and simulation, automated code generation and coverage analysis between the model and the generated source codes. The "3-Step" safety analysis consists of HAZOP (hazard and operability analysis), FTA (fault tree analysis), and DV (design validation). Put together, these steps are called the "3+3 Process". This scheme of development and safety analysis minimizes the V&V work while increasing the safety and reliability of the software product. For assessment of this process, validation has been done through prototyping of the SDS (safety shut-down system) #1 for PHWR (Pressurized Heavy Water Reactor).

• 전자공학회논문지 IE
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• v.45 no.3
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• pp.5-12
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• 2008

We propose efficient scan testing method capable of reducing the test data and power dissipation for digital logic circuits. The proposed testing method is based on a hybrid run-length encoding which reduces test data storage on the tester. We also introduce modified Bus-invert coding method and scan cell design in scan cell reordering, thus providing increased power saving in scan in operation. Experimental results for ISCAS'89 benchmark circuits show that average power of 96.7% and peak power of 84% are reduced on the average without fault coverage degrading. We have obtained a high reduction of 78.2% on the test data compared the existing compression methods.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.832-841
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• 2016

The voltage-frequency island (VFI) design paradigm has strong potential for achieving high energy efficiency in communication centric manycore system-on-chip (SoC) design called network-on-chip (NoC). However, because of the diminished scaling of wire-dimension and supply voltage as well as threshold voltage in modern CMOS technology, the vulnerability to link failure in VFI NoC is becoming a crucial challenge. In this paper, we propose an energy-optimized topology generation technique for VFI NoC to cope with permanent link failures. Based on the energy consumption model, we exploit the on-chip communication traffic patterns and characteristics of link failures in the early design stage to accommodate diverse applications and architectures. Experimental results using a number of multimedia application benchmarks show the effectiveness of the proposed three-step custom topology generation method in terms of energy consumption and latency without any degradation in the fault coverage metric.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.9
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• pp.1395-1403
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• 1993

Protocol conformance is crucial to inter-operability and cost effective computer communication. Given a protocol specification, the task of checking whether an inplementation conforms to the specification is called conformance testing. The efficiency and fault coverage of conformance testing are largely dependent on how test cases are chosen. Some states may have more one UIO sequence when the protocol is represented by FSM (Finite State Machine). The length of test sequence can be minimized if the optimal test sequences are chosen. In this paper, we construct the depth-tree to find the maximum overlapping among the test sequence. By using the resulting depth-tree, we generate the minimum-length test sequence. We show the example of the minimum-length test sequence obtained by using the resulting depth-tree.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.1
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• pp.396-413
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• 2017

Dynamically checking the integrity of software at run-time is always a hot and difficult spot for trusted computing. Control-flow integrity is a basic and important safety property of software integrity. Many classic and emerging security attacks who introduce illegal control-flow to applications can cause unpredictable behaviors of computer-based systems. In this paper, we present a software-based approach to checking violation of control flow integrity at run-time. This paper proposes a high-performance and low-overhead software control flow checking solution, control flow checking at virtual edges (CFCVE). CFCVE assigns a unique signature to each basic block and then inserts a virtual vertex into each edge at compile time. This together with insertion of signature updating instructions and checking instructions into corresponding vertexes and virtual vertexes. Control flow faults can be detected by comparing the run-time signature with the saved one at compile time. Our experimental results show that CFCVE incurs only 10.61% performance overhead on average for several C benchmark programs and the average undetected error rate is only 9.29%. Compared with previous techniques, CFCVE has the characteristics of both high fault coverage and low memory and performance overhead.

• The Transactions of the Korea Information Processing Society
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• v.5 no.6
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• pp.1633-1638
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• 1998

In this paper we propose a generic BIST builder for the Embedded Multiple HAM modules in ASICs, The BlST circuitry is automatically generated according to the specification of the target RAM Modules and the applying test algorithms to them. The lJIST is designed using the TOP-DOWN technique and, thus, has the several advantages in the area of the selection of test algorithm, the development of the circuitry, and the reuse of the circuitry, In addition, we have modified the existing serial interiacing approach to obtain smaller additional BlST circuitry and higher fault coverage and better B1ST sharing of the target RAM Modules in ASICs.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.29-37
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• 1998

In weighted random pattern testing it is an important issue to find the optimal weight sets for achieving a high fault coverage using a small number of weighted random patterns. In this paper, a new weight set optimization algorithm is developed, which can generate the optimal weight sets in an efficient way using the sampling probabilities of deterministic tests patterns. In addition, the simulation based method of finding the proper maximum Hamming distance is presented. Experimental results for ISCAS 85 benchmark circuits prove the effectiveness of the new weight set optimization algorithm and the method of finding the proper maximum Hamming distance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.30-37
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• 2006

This paper presents a modified scan cell architecture to reduce the power dissipation during testing. It not only eliminates switching activities in the combinational logic during scan shifting but also reduces switching activities in the scan chain during the time. Furthermore, it limits the transitions on capture cycles. It can be made for test-per-scan BIST and employed in both single scan style and multiple scan style. Experimental results demonstrate that the proposed structure achieves the same fault coverage with lower power consumption compared to other existing BIST schemes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.10 s.340
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• pp.47-54
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• 2005

In this paper, a new synthesis method for testability of synchronous sequential circuits is suggested on an incompletely-specified state transition graph (STG) by reducing the number of redundant faults. In the suggested synthesis method, 1) a given STG is modified by adding undefined states and unspecified input transitions using distinguishable transition, 2) the STG is modified to be strongly-connected as much as possible. Experimental results with MCNC benchmark show that the number of redundant faults of gate-level circuits synthesized by our modified STGs are reduced, and much higher fault coverage is obtained.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.44-52
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• 2002

Since memory technology has been developed fast, test complexity and test time have been increased simultaneously. In practice, March algorithms are used widely for detecting various faults. However, March algorithms cannot detect NPSFs(Neighborhood Pattern Sensitive Faults) which must be considered for DRAMs. This paper proposes an effective algorithm for high fault coverage by modifying the conventional March algorithms.