• Korean Journal of Optics and Photonics
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• v.33 no.3
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• pp.106-112
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• 2022

A two-dimensional optical code division multiple access (OCDMA) encoder/decoder, which is composed of add/drop filters and all-pass filters for delay operation, is proposed. An example design is presented, and its feasibility is illustrated through numerical simulations. The chip area of the proposed OCDMA encoder/decoder could be about one-third that of a previous OCDMA device employing delay waveguides. Its performance is numerically investigated using the transfer-matrix method combined with the fast Fourier transform. The autocorrelation peak level over the maximum cross-correlation level for incorrect wavelength hopping and spectral phase code combinations is greater than 3 at the center of the correctly decoded pulse, which assures a bit error rate lower than 10^-3, corresponding to the forward error-correction limit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.61-68
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• 2005

A chip, which can fast encoder the audio data to AAC (Advanced Audio Coding) LC(Low Complexity) that is MPEG-2 audio standard, has been designed on the basis of a 32 bits DSP core and fabricated with 0.25um CMOS technology. At first, the various optimization methods for implementing the algerian are devised to reduce the memory size and calculation cycles. FFT(Fast Fourier Transform) hardware block is added to the DSP core to get the more reduction of the calculation cycles. The chips has the size of $7.20\times7.20 mm^2$ and about 830,000 equivalent gates, can carry out AAC encoding under 70MIPS(Million Instructions per Second).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.42-49
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• 2007

CABAC(Context-based Adaptive Binary Arithmetic Coding) among various entropy coding schemes which are used to improve compression efficiency in H.264/AVC has a high hardware complexity and the fast calculation is difficult because data dependancy exists in the bit-serial process. In this paper, the proposed architecture efficiently compose the renormalization process of binary arithmetic encoder which is an important part of CABAC used in H.264/AVC. At every clock cycle, the input symbol is encoded regardless of the iteration of the renormalization process for every input symbol. Also, the proposed architecture can deal with the bitsOutstanding up to 127 which is adopted to handle the carry generation problem and encode input symbol without stall. The proposed architecture with three-stage pipeline has been synthesized using the 0.18um Dongbu-Anam standard cell library and can be operated at 290MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.34-40
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• 2010

This paper proposes an efficient CABAC encoder to reduce syntax element storage in H.264/AVC entropy coding. In the proposed architecture, all blocks are designed in dedicated hardware, so it performs fast processing without programmable processors. Context modeler of CABAC encoder requires the neighbor block data. However it requires impractically huge memory size if the neighbor block data is directly stored without proper processing. Therefore, this paper proposes an effective method of storing the neighbor block data to decrease memory size. The proposed CABAC encoder has 35,463 gates in 0.18um standard cell library. It operates at maximum speed of 180MHz and its throughput is about 1 cycle per input symbol.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.561-564
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• 2004

The motion estimation which requires huge computation consumes large power in a video encoder. Although a number of fast-search algorithms are proposed to reduce the power consumption, the smaller the computation, the worse the performance they have. In this paper, we propose an architecture that a low energy management scheme can be applied with several fast-search algorithm. In addition. we show that ECVH, a software scheduling scheme which dynamically changes the search algorithm, the operating frequency, and the supply voltage using the remaining slack time within given power-budget, can be applied to the architecture, and show that the power consumption can be reduced.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.594-600
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• 2017

This paper proposes a global search based motion estimation algorithm for high performance HEVC encoder and its hardware architecture. To eliminate temporal redundancy, motion estimation in HEVC inter-view prediction uses global search and fast search algorithm to search for a predicted block having a high correlation with the current PU in an interpolated reference picture. The global search method predicts the motion of all candidate blocks in a given search area, thus ensuring optimal results, but has a disadvantage of large computation time. Therefore we propose a new algorithm that reduces computational complexity by reusing SAD operation in global search to reduce computation time of inter prediction. As a result of applying the proposed algorithm to standard software HM16.12, the computation time was reduced by 61%, BDBitrate by 11.81%, and BDPSNR by about 0.5% compared with the existing search algorithm. As a result of hardware design, the maximum operating frequency is 255 MHz and the total number of gates is 65.1K.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.2
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• pp.139-144
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• 2011

The modern digital logic technology does not yet satisfy the speed requirements of real-time DSP circuits due to synchronized operation of multiplication and accumulation. This operation degrades DSP performance. Therefore, the double-base number system (DBNS) has emerged in DSP system as an alternative methodology because of fast multiplication and hardware simplicity. In this paper, authors propose a novel multiplication architecture. One operand is an output of a flash analog-to-digital converter (ADC) in DBNS format, while the other operand is a coefficient in the IEEE standard floating-point number format. The DBNS digital output from ADC is produced through a new double base number encoder (DBNE). The multiplied output is in the format of the IEEE standard floating-point number (FPNS). The proposed circuits process multiplication and conversion together. Compared to a typical multiplier that uses the FPNS, the proposed multiplier also consumes 45% less gates, and 44% faster than the FPNS multiplier on Spartan-3 FPGA board. The design is verified with FIR filter applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.66-72
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• 2009

This paper proposes an efficient binary arithmetic encoder for CABAC which is used one of the entropy coding methods for H.264/AVC. The present binary arithmetic encoding algorithm requires huge complexity of operation and data dependency of each step, which is difficult to be operated in fast. Therefore, renormalization exploits 2-stage pipeline architecture for efficient process of operation, which reduces huge complexity of operation and data dependency. Context model updater is implemented by using a simple expression instead of transIdxMPS table and merging transIdxLPS and rangeTabLPS tables, which decreases hardware size. Arithmetic calculator consists of regular mode, bypass mode and termination mode for appearance probability of binary value. It can operate in maximum speed. The proposed binary arithmetic encoder has 7282 gate counts in 0.18um standard cell library. And input symbol per cycle is about 1.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1995.10a
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• pp.985-990
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• 1995

Recently, the development of high speed and high precision NC-lathe for piston head machining is needed for the complexity and diversity of the piston head shape used in automobile reciprocating engine. THe piston head has many complex shapes in the aspect of fuel economy, such as ovality, profile, double ovality and recess. Among them, for the maching of the over shape of 0.1~1mm the cutting tool should move periodically symchronized with the rotation of piston workpiece. The cutting tool feeed system must have high positioning accuracy for the precise machining, high speed for the fast maching and high dynamic stiffness for the cutting force. The linear brushless DC motor is used for satisfying these coditions. The ballbush guide and supporting guide using turcite is used for the guidance of the feed drive system. Linear encoder, digital servo ampllifer and controller are used for driving the motor. THis paper presents the design and simulation of the new tool feed system for noncircular machining.

• Proceedings of the KIEE Conference
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• 1987.11a
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• pp.355-358
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• 1987

A design of digital position control system with DC Motor is presented. The digital position control system is constructed by power circuits, interface circuits and control circuits using single chip microprocessor (8096). All control functions are implemented on the 16 bit micro-processor requiring only on incremental encoder for speed and position sensing. The control schemes are used by the proportional control for some modifications and braking algorithms. This digital position system offered to the fast response, good steady-state accuracy, flexibility and reliability, Hardware, software features and experimental results of this system are described.