• Journal of Power Electronics
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• v.11 no.4
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• pp.520-526
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• 2011

This paper presents a balanced soft-chopping circuit and a modified PI controller for a high speed 4/2 Switched Reluctance Motor (SRM) with a 16 pulse per revolution encoder. The proposed balanced soft-chopping circuit can supply double the switching frequency in the fixed switching frequency of power devices to reduce current ripple. The modified PI controller uses maximum voltage, back-emf voltage and PI control modes to overcome the over-shoot current due to the time delay effect of current sensing. The maximum voltage mode can supply a fast excitation current with consideration of the hardware time delay. Then the back-emf voltage mode can suppress the current over-shoot with consideration of the feedback signal delay. Finally, the PI control mode can adjust the phase current to a desired value with a fast switching frequency due to the proposed balanced soft-chopping technology.

• International Journal of Precision Engineering and Manufacturing
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• v.8 no.2
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• pp.20-25
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• 2007

This paper describes a second-generation dual sine-grid surface encoder for 2-D position measurements. The surface encoder consisted of a 2-D grid with a 2-D sinusoidal pattern on its surface, and a 2-D angle sensor that detected the 2-D profile of the surface grid The 2-D angle sensor design of previously developed first-generation surface encoders was based on geometric optics. To improve the resolution of the surface encoder, we fabricated a 2-D sine-grid with a pitch of $10{\mu}m$. We also established a new optical model for the second-generation surface encoder that utilizes diffraction and interference to generate its measured values. The 2-D sine-grid was fabricated on a workpiece by an ultra precision lathe with the assistance of a fast tool servo. We then performed a UV-casting process to imprint the sine-grid on a transparent plastic film and constructed an experimental setup to realize the second-generation surface encoder. We conducted tests that demonstrated the feasibility of the proposed surface encoder model.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.260-264
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• 2013

This paper proposes a fast enhancement layer coding method to reduce computational complexity for Scalable HEVC (SHVC) which is based on High Efficiency Video Coding (HEVC). The proposed method decreases encoding time by simplifying Rate Distortion Optimization (RDO)for enhancement layers (EL). The simplification is achieved by restricting CU depths based on the correlation of coding unit (CU) depths between adjacent layers and scalability (spatial or quality) of EL. Comparing with the performance of SHM 1.0 software encoder, the proposed method reduces the encoding time by up to 31.5%.

• ETRI Journal
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• v.35 no.2
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• pp.270-280
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• 2013

A fast intra-prediction method is proposed for High Efficiency Video Coding (HEVC) using a fast intra-mode decision and fast coding unit (CU) size decision. HEVC supports very sophisticated intra modes and a recursive quadtree-based CU structure. To provide a high coding efficiency, the mode and CU size are selected in a rate-distortion optimized manner. This causes a high computational complexity in the encoder, and, for practical applications, the complexity should be significantly reduced. In this paper, among the many predefined modes, the intra-prediction mode is chosen without rate-distortion optimization processes, instead using the difference between the minimum and second minimum of the rate-distortion cost estimation based on the Hadamard transform. The experiment results show that the proposed method achieves a 49.04% reduction in the intra-prediction time and a 32.74% reduction in the total encoding time with a nearly similar coding performance to that of HEVC test model 2.1.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.5
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• pp.417-425
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• 2003

H.264, which is the latest video coding standard of both ITU-T(International Telecommunication Union-Telecommunication standardization sector) and MPEG(Moving Picture Experts Group), adopts new video coding tools such as variable block size motion estimation, multiple reference frames, quarter-pel motion estimation/compensation(ME/MC), 4${\times}$4 Integer DCT(Discrete Cosine Transform), and Rate-Distortion Optimization, etc. These new video coding tools provide good coding of efficiency compared with existing video coding standards as H.263, MPEG-4, etc. However, these new coding tools require the increase of encoder complexity. Therefore, in order to apply H.264 to many real applications, fast algorithms are required for H.264 coding tools. In this paper, when encoder MacroBlock(MB) mode is decided by rate-distortion optimization tool, fast mode decision algorithm by skipping variable block size ME/MC and spatial-predictive coding, which occupies most encoder complexity, is proposed. In terms of computational complexity, the proposed method runs about 4 times as far as JM(Joint Model) 42 encoder of H.264, while the PSNR(peak signal-to-noise ratio)s of the decoded images are maintained.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.5
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• pp.285-290
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• 2012

In this paper, we propose a fast encoding algorithm for scalable video encoding without compromising coding performance. Through analysis on multiple motion estimation processes performed at the enhancement layer, we show redundant motion estimations and suggest the condition under which the redundant ones can efficiently be determined without additional memory. Based on the condition, the redundant motion estimation processes are excluded in the proposed algorithm. Simulation results show that the proposed algorithm is faster than the conventional fast encoding method without performance degradation and additional memory.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04a
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• pp.13-15
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• 2003

본 논문은 FastImage1300가 제공하는 병렬처리 구조를 사용하여 최적의 MPEG-4 부호화기를 구현하기 위한 프로세서 및 데이터 관리 방법을 제시한다. MPEG-4 부호화기가 가진 병렬성과 순차성을 FastImage1300 특성에 맞추어서 이 시스템이 제공할 수 있는 최대 속도로 동작하는 MPEG-4 부호화기를 구현한다. 이 부호화기를 사용하여 CIF 영상을 MPEG-4 CP@L3로 최대 25fps까지 부호화 할 수 있다.

• Journal of the Institute of Convergence Signal Processing
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• v.14 no.4
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• pp.249-254
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• 2013

A fast multiplier and ADC are essential to process the analog signals in real time. The double-base number system(DBNS) is known as an efficient method for this purpose. The DBNS uses the numbers 2 and 3 as the base numbers simultaneously. The system has an advantage of fast multiplication, less chip area, and low power consumption compared to the binary multiplier. However, the inherent errors of the log number's intrinsic tolerance in DBNS are accumulated in a FIR digital filter, so the signal-to-noise ratio(SNR) has a tendency to be degraded. In this paper, the nonlinear encoder of ADC is designed to compensate the accumulated errors of DBNS by analysing the error distributions of various filter coefficients. The new ADC does not sacrifice its own advantages because the encoder circuits are modified only. The experiments were done with an FIR filters those were designed to have -70dB of SNR in stop band. The proposed nonlinear ADC encoder could drop the SNR to -45dB in stop band, in contrast to -35dB with the linear encoder.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.7
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• pp.1-8
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• 2008

Low Density Parity Check codes(LDPC) are recently focused on communication systems due to its good performance. The standard of WiBro has also included LDPC codes as a channel coding. The weak point of implementation for LDPC encoder is that conventional binary Matrix Vector Multiplier has many clock cycles which limit throughput. In this paper, we propose semi-parallel architecture by using cyclic shift registers and exclusive-OR without conventional Matrix Vector Multipliers over the standard parity check matrices with Circulant Permutation Matrices(CPM). Furthermore, multi-rate encoder is designed by using proposed architecture. Our encoder with multi-rate for IEEE 802.16e LDPC has lower clock cycles and higher throughput.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.10C
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• pp.968-974
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• 2009

In this paper, we present a skipping method of transformation and quantization process using skip blocks estimation in fast H.264 video encoder. In order to reduce the complexity, we estimate skip mode blocks using integer discrete cosine transform and quantization and a skipping condition is derived by the analysis of those processes. The experimental result show that the proposed algorithm has effective estimations.