• 한국군사과학기술학회지
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• 제13권5호
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• pp.775-784
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• 2010

In this paper we propose a design method of X band frequency hopping synthesizer in terms of phase noise and settling time with DDS driven PLL architecture, which has the advantages of high frequency resolution, fast settling time and small size. In addition, a noble method is proposed to remove the synthesizer output spurious signals due to superposition effect of DDS. The spurious signal which depend on its normalized frequency of DDS, can be dominant if they occur within the PLL loop bandwidth. We verify that the sources of that spurious signals are quasi-amplitude modulation and superposition effect, and suggest that such signals can be eliminated by intentionally creating frequency errors in the developed synthesizer.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.607-608
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• 2006

A CMOS phase-locked loop (PLL) which synthesizes frequencies between $6.336{\sim}8.976GHz$ in steps of 528MHz and settles in approximately 150ns using the 528MHz reference clock is presented. Frequency hopping between the bands in the each mode is critical point to design the PLL in multi-band orthogonal frequency division multiplexing (OFDM) because frequency switching between each band is less than 9.5ns. To achieve the fast loop settling, integer-N PLL that operates with the high reference frequency to meet the settling requirement is implemented. Two PLLs that operate at 9GHz and 528MHz is integrated and shows the band hopping lower than 1ns.

• 한국정보통신학회논문지
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• 제13권8호
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• pp.1543-1548
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• 2009

본 논문에서는 주파수 도약 대역 확산시스템에서 빠른 주파수 도약 패턴을 발생시키며 이에 따른 수신기 동기회로에 관한 연구이다. 고속의 PN 초기동기를 달성하기 위한 정합필터 방식에서 기존의 동기회로 구조로부터 상관기의 개수를 2개로 줄이고 초기동기를 위한 짧은 도약패턴(hoping prefix)을 몇 개의 부 패턴(sub prefix)으로 나눈다. 각기 상이한 주파수 도약패턴에 의하여 PN코드 시작시각에 대한 정보를 보내 이 정보를 이용하여 빠른 동기 획득을 이루게 하며 검출의 신뢰도를 높일 수 있는 고속의 초기동기 회로를 제안하였다. 또한 디지털 주파수 합성기를 사용하여 빠른 주파수 도약을 위한 PLL 구현이 가능함을 분석하였다. 즉, 주파수 스텝(${\Delta}f$)이 1.5MHz이상이면 settling 시간이 $30{\mu}s$정도가 되므로 빠른 주파수 도약을 위한 PLL의 구현이 가능함을 보였다. 결국 동기시간 단축에 있어서 가장 큰 영향을 미치는 것은 주파수 합성기의 빠른 주파수 획득시간과 동기회로의 초기동기 획득시간임을 알 수 있었다.

• 디지털산업정보학회논문지
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• 제8권3호
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• pp.65-74
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• 2012

A barcode is a representative means of cognition. It is either printed on the package of a product or attached to it as a sticker. It is used for the fast cognition of a product at a store. It is considerably cheap to make a barcode. Also, it is possible to read it fast by using a barcode reader. Because of such convenience provided by the barcode, a new system using the barcode as a means of settling payments like a currency or a credit card has been developed. However, due to its characteristics, it is easy to reduplicate, forge or falsify a barcode easily. Therefore, this study focuses on the case of applying the system using barcodes as a means of settling payments without providing solutions for the potential weaknesses. Also, this study suggests various points to consider regarding the creation of safe barcodes as one of the related measures, while providing various methods using additional means of certification other than the one of using barcodes in addition to the way of applying complexity with barcode numbers. Throughout this study, it will be possible to safely establish and operate the payment-settlement system using barcodes.

• 한국전자파학회논문지
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• 제25권12호
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• pp.1251-1257
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• 2014

본 논문에서는 6~13 GHz 주파수 범위에서 30 kHz 이하의 주파수 분해능과 500 ns 이하의 동조 속도를 갖는 광대역 고속 주파수 합성기 구조를 제안하였다. 광대역에서 빠른 동조 속도와 우수한 위상잡음 특성, 고해상도 주파수 특성을 얻기 위해 DDS(Direct Digital Synthesizer)와 아날로그 직접 주파수 합성기술을 적용하여 주파수 합성기의 출력을 합성하였다. 그리고 광대역 주파수 합성기의 위상잡음 특성을 중첩의 원리를 이용하여 예측하였고 측정 결과와 비교하였다. 제작된 주파수 합성기의 주파수 동조 속도는 500 ns 이하, 위상잡음은 최고 주파수에서 -106 dBc @ 10 kHz 이하, 주파수 정확도는 ${\pm}2kHz$ 이하로 측정 되었다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1999년도 전력전자학술대회 논문집
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• pp.80-83
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• 1999

The windup phenomenon appears and results in performance degradation such as large overshoot, slow settling time when the integral-proportional (IP) controller output is saturated. An anti-windup IP controller is proposed to improve the control performance for the motor drives. The proposed algorithm is applied to the current control of a vector-controlled induction motor driven by a pulse width modulated(PWM) voltage-source inverter. The integral state is separately controlled corresponding to whether the IP controller output is saturated or not. The experimental results show that the current response has much improved performance such as little overshoot and fast settling time.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1996년도 추계학술대회 논문집
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• pp.820-825
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• 1996

This paper is concerned with effective operating method of pneumatic on-off valves for improving position control accuracy, valve life-time and position settling time using modified pulse width modulation with dead-zone. The pneumatic system using on-off valves studied in this paper has advantage of simple construction and low cost compared with a system with servo-valves. The performance of proposed control system is investigated experimentally for the position control of a pneumatic cylinder using on-off valves. Experimental results show that the proposed algorithm for valve operation can be used to obtain fast and accurate position control and to prevent on-off valves from unnecessary switching.

• 대한전기학회논문지:시스템및제어부문D
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• 제51권6호
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• pp.252-257
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• 2002

We designed a neuro-fuzzy controller to improve some problems that are happened when the DC servo motor is controlled by a PID controller or a fuzzy logic controller. Our model proposed in this paper has the stable and accurate responses, and shortened settling time. To prove the capability of the neuro-fuzzy controller designed in this paper, the proposed controller is applied to the speed control of DC servo motor. The results showed that the proposed controller did not produce the overshoot, which happens when PID controller is used, and also it did not produce the steady state error when FLC is used. And also, it reduced the settling time about 10%. In addition, we could by aware that our model was only about 60% of the value of current peak of PID controller.

• Journal of Electrical Engineering and Technology
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• 제6권5호
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• pp.658-665
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• 2011

In the present paper, a novel fast peak detector for single- or three-phase unsymmetrical voltage sags is proposed. The proposed detector is modified from a single-phase digital phase-locked loop based on a d-q transformation using an all-pass filter (APF). APF generates a virtual phase with $90^{\circ}$ phase delay. However, this virtual phase cannot reflect a sudden change of the grid voltage in the moment of voltage sag, which causes a peak value to be significantly distorted and to settle down slowly. Specifically, the settling time of the peak value is too long when voltage sag occurs around a zero crossing, such as phase $0^{\circ}$ and $180^{\circ}$. This paper describes the operating principle of the APF problem and proposes a modified all-pass filter (MAPF) to mitigate the inherent APF problem. In addition, a new fast peak detector using MAPF is proposed. The proposed detector is able to calculate a peak value within 0.5 ms, even when voltage sag occurs around zero crossing. The proposed fast peak detector is compared with the conventional detector using APF. Results show that the proposed detector has faster detection time in the whole phase range. Furthermore, the proposed fast peak detector can be effectively applied to unsymmetrical three-phase voltage sags. Simulation and experimental results verify the advantages of the proposed detector and MAPF.

• 한국진공학회지
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• 제5권4호
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• pp.284-291
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• 1996

차세대 반도체 제조공정을 위한 고진공 클러스터 장비용 반송모듈에 대해 고속 응답이 가능한 압력제어 장치의 구현과 그 성능시험을 수행하였다. 일반적인 자동 유량조절기가 가지고 있는 저속 응답에 대한 문제점을 해결하기 위하여 압력제어 순서를 매우 효과적으로 최적화하기 위하여 새로운 실험방법이 제시되었다. 압력제어를 시작하는 시점과 Ziegler-Nichols 제어방법에 의한 조율 상수들을 조절함으로써 매우 안정되고 빠른 응답이 가능한 압력제어를 성공적으로 달성하였다. 반송압력이 $10\times 10^{-5}$ torr인 경우, 질소의 초기유량을 21 sccm으로 설정한 수 4초 시각부터 실제적인 압력제어가 시작되었다. 그 결과, 최대 압력오차가 설정값에 대해 $\pm$0.5% 이하에서 안정화 시간은 10 sec 이내로 기존 실험방법과 비교해 볼 때 70% 정도 개선된 우수한 성능을 얻을 수 있었다. 이때 rise rate는 0.02 torr/sec, the lag time는 0.15sec, the sampling period는 0.5 sec이였다. 이러한 실험결과를 설명하기 위하여 이론적인 모델이 유도되었으며, $\omega$=-1.0일 때 실험결과와 잘 일치함을 알 수 있었다.