• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.163-175
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• 1996

This paper invetigates estimation methods of mapping parameters in object-oriented coding. In this paper, we propose a fast parameter estimation method with its performance similar to that of the conventional methods. We employ hierarchical structure in difference images to redcue the computational complexity and also combine conventional six- and eight-mapping parameter estimation methods to compensate for the performance degradation caused by employment of hierarchical structure. Computer simulation shows that the proposed mehtod gives results similar to conventional methods with greatly reduced computational complexity.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.79-85
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• 2010

In video standards such as H.264/AVC, motion estimation (ME) / compensation (MC) is regarded as a vital component in a video coder as it consumes a large amount of computation resources. The full search technique, which is used in general video codecs, gives the highest visual quality but also has the problem of significant computational load. To solve this problem, many fast algorithm has benn proposed. Among them, NPDS show that can maintain its video quality very close to the full search technique while achieving computation reduction by using a halfway-stop technique in the calculation of block distortion measure. In this paper, we proposed algorithm by determining minimum distortion measure with predictive motion vector and using the new search order. As the result, we can check that the proposed algorithm reduces the computational load 95% in average compared to the full search, respectively with the PSNR lost about 0.04dB.

• ETRI Journal
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• v.32 no.4
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• pp.577-587
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• 2010

The layered coding structure of scalable video coding (SVC) with adaptive inter-layer prediction causes noticeable computational complexity increments when compared to existing video coding standards. To lighten the computational complexity of SVC, we present a fast algorithm to speed up the inter-mode decision process. The proposed algorithm terminates inter-mode decision early in the enhancement layers by estimating the rate-distortion (RD) cost from the macroblocks of the base layer and the enhancement layer in temporal, spatial, and inter-layer directions. Moreover, a search range decision algorithm is also proposed in this paper to further increase the motion estimation speed by using the motion vector information from temporal, spatial, or inter-layer domains. Simulation results show that the proposed algorithm can determine the best mode and provide more efficient total coding time saving with very slight RD performance degradation for spatial and quality scalabilities.

• Journal of IKEEE
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• v.16 no.4
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• pp.382-388
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• 2012

An H.264/AVC fast motion estimation methodology is presented in this paper. Advanced SIMD based NEON which is one of the parallel processing methods is supported under the ARM Cortex-A9 dual-core platform. NEON is applied to a full search technique with one of the various motion estimation methods and SAD operation count of each macroblock is reduced to 1/4. Pixel values of the corresponding macroblock are assigned to eight 16-bit NEON registers and Intrinsic function in NEON architecture carried out 128 bits arithmetic operations at the same time. In this way, the exact motion vector with the minimum SAD value among the calculated SAD values can be designated. Experimental results show that performance gets improved 30% above average in accordance with the size of image and macroblock.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.107-108
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• 2012

For low complexity encoder, the parity bit transmission through a feedback channel is an essential part of DVC. But feedback channel-based parity bit control is a major cause for the high decoding time latency. In this paper, we propose a fast distributed video decoding by parity bit request estimation using rate-distortion model. Through computer simulations, it is shown that the proposed method can achieve complexity reduction compared to other methods.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.5
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• pp.509-517
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• 2001

Full-search algorithm requires large amount of computation which causes time delay or very complex hardware architecture for real time implementation. In this paper, we propose a fast motion estimator based on bit-plane matching, which reduce the computational complexity and the hardware cost. In the proposed motion estimator, the conventional motion estimation algorithms are applied to the binary images directly extracted from the video sequence. Furthermore, in the proposed VLSI motion estimator, we employ a Pair of processing cores that calculate the motion vector continuously By controlling the data flow in a systolic fashion using the internal shift registers in the processing cores, we avoid using SRAM (local memory) so that we remove the time overhead for accessing the local memory and adopt lower-cost fabrication technology. We modeled and tested the proposed motion estimator in VHDL, and then synthesized the whole system which has been integrated in a 0.6-$\mu$m triple-metal CMOS chip of size 8.15 X 10.84$\textrm{mm}^2$.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.717-720
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• 1998

In this paper, we propose a VLSI architecture for implementing a crecently proposed fast block matching algorithm, which is called the HSBMA3S. The proposed architecture consists of a systolic array based basic unit and two shift register arrays. And it covers a search range of -32 ~+31. By using a basic unit repeatedly, we can redcue the number of gates. To implement the basic unit, we can select one among various conventional systolic arrays by trading-off between speed and hardware cost. In this paper, the architecture for the basic unit is selected so that the hardware cost can be minimized. The proposed architecture is fast enough for low bit-rate applications (frame size of 352x288, 30 frames/sec) and can be implemented by less than 20,000 gates. Moreover, by simply modifying the basic unit, the architecture can be used for the higher bit-rate application of the frame size of 720*480 and 30 frames/sec.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.4
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• pp.231-234
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• 2016

The next-generation video coding standard known as High-Efficiency Video Coding (HEVC) was developed with the aim of doubling the bitrate reduction offered by H.264/Advanced Video Coding (AVC) at the expense of an increase in computational complexity. Mode decision with motion estimation is still one of the most time-consuming computations in HEVC, as it is with H.264/AVC. Several schemes for a fast mode decision have been presented in reference software and in other studies. However, a possible speed-up in conventional schemes is sometimes insignificant for videos that have inhomogeneous spatial and temporal characteristics. This paper proposes a bypass algorithm to skip large-block-size predictions for videos where small block sizes are preferred over large ones. The proposed algorithm does not overlap with those in previous works, and thus, is easily used with other fast algorithms. Consequently, an independent speed-up is possible.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.9
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• pp.86-94
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• 1998

This paper proposes a new fast block-matching algorithm, named MFSS(Modified Four-Step Search) algorithm, which has better performance and is more adequate for hardware realization than the existing fast algorithms. The proposed algorithm is suitable for hardware realization since it has a unique regularity during the search procedure. It is shown from simulation results that its performance is close to that of FS(Full Search) algorithm. This paper also proposes a VLSI architecture and presents some design results of a motion estimator and compensator which adopted the MFSS algorithm. The important aspects considered in designing a motion estimator and compensator are hardware complexity of design results, and total delay needed to generate the motion compensated data after finding the motion vectors. Hardware complexity is minimized by using just nine PE(Process Element)'s, and total delay is minimized by sharing search memory of the motion estimator and compensator.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.10
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• pp.36-42
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• 1997

In the whole world, the research about the VLSI implementation of motion estimation algorithm is progressed to actively full (brute force) search algorithm research with the development of systolic array possible to parallel and pipeline processing. But, because of processing time's limit in a field to handle a huge data quantily such as a high definition television, many problems are happened to full search algorithm. In the paper, as a fast processing to using parallel scheme for the serial input image data, motion estimator of systolic array structure verifying that processing time is improved in contrast to the conventional full search algorithm.