• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.607-610
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• 1998

The major objectives of speech coding include high compression ratio for transmission in the band limited channel, high synthesized speech quality in terms of the intelligibility and the naturalness and fast processing speed. In general, speech coding methods are classified into the following three categories: the wavelform coding, the source coding and the hybird coding. In this paper, we proposed a new waveform coding method using PSOLA(pitch-synchronous overlap add) technique. First, we fixed one basic waveform per pitch and measured the formant similarity between basic and neighbor waveform. Second, if the similairy satisfied threshold values, we compress the neighbor waveform per pitch and then store or transmit. When the comparession is about 45%, we obtained about 4 in MOS.

• Genomics & Informatics
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• v.3 no.1
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• pp.39-42
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• 2005

DNA microarray is a high-throughput biomedical technology that monitors gene expression for thousands of genes in parallel. The abundance and complexity of the gene expression data have given rise to a requirement for their systematic management and analysis to support many laboratories performing microarray research. On these demands, we developed Xperanto for integrated data management and analysis using user-friendly web-based interface. Xperanto provides an integrated environment for management and analysis by linking the computational tools and rich sources of biological annotation. With the growing needs of data sharing, it is designed to be compliant to MGED (Microarray Gene Expression Data) standards for microarray data annotation and exchange. Xperanto enables a fast and efficient management of vast amounts of data, and serves as a communication channel among multiple researchers within an emerging interdisciplinary field.

• Journal of Communications and Networks
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• v.15 no.5
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• pp.538-542
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• 2013

This paper proposes a broadcast software download (BSD) scheme for a 10-gigabit-capable passive optical network (XG-PON), which dramatically reduces the time required to update a remotely-located user terminal's software. The performance of the proposed BSD is examined by numerical analysis and demonstrated by experimental verification on our XG-PON test platforms. The results show that the BSD takes less than 5 minutes to update 45 user-terminal software, while the conventional unicast software download scheme normally takes more than one and half hours.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.6
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• pp.1040-1048
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• 1987

We propose a hardware architecture called Multiring which is applicable for various geometrical operations on rectilinear objects such as design rule checking in VLSI layout and many image processing operations including noise suppression and coutour extraction. It has both a fast execution speed and extremely high flexibility. The whole architecture is mainly divided into four parts` I/O between host and Multiring, ring memory, linear processor array and instruction decoder. Data transmission between host and Multiring is bit serial thereby reducing the bandwidth requirement for teh channel and the number of external pins, while each row data in the bit map stored in ring memory is processed in the corresponding processor in full parallelism. Each processor is simultaneously configured by the instruction decoder/controller to perform one of the 16 basic instructions such as Boolean (AND, OR, NOT, and Copy), geometrical(Expand and Shrink), and I/O operations each ring cycle, which gives Multiring maximal flexibility in terms of design rule change or the instruction set enhancement. Correct functional behavior of Multiring was confirmed by successfully running a software simulator having one-to-one structural correspondence to the Multiring hardware.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.6
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• pp.1074-1079
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• 1987

We present a fast, constructive algorithm for the automatic placement of standard cells, which consists of two steps. The first step is responsible for cell-row assignment of each cell, and converts the circuit connectivity into a multi-stage graph under to constraint that sum of the cell-widths in each stage of the multi-state graph does not exceed maximum cell-row width. Generatin of feed-through cells in the final layout was shown to be drastically reduced by this step. In the second step, the position of each cell within the row is determined one by one from left to right so that the cost function such as the local channel density is minimized. Our experimental result shows that this algorithm yields near optimal results in terms of the number of feed-through cells and the horizontal tracks, while running about 100 times faster than other iterative procedures such as pairwise interchange and generalized force directed relaxation method.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.86-89
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• 1999

In this paper, we propose a new architecture of the fast symbol timing synchronization system which has some shared hardware blocks in order to reduce the hardware complexity. The proposed system consists of received power detector, correlation power detector using shared complex moving adders, and 2-step peak detector. Our system has detected FFT starting point within three Symbols using first two reference symbols of the frame in wireless ATM system. The new architecture was designed and simulated using VHDL. Our proposed architecture also detects a correct symbol timing synchronization within three symbols under a multi-path fading channel.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.5
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• pp.1-13
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• 1995

In this paper, we evaluated the mean acquisition time and it's variance of the rapid synchronization system using the DMF(Digital Matched Filter) under the DS/CDMA system which uses the long period PN code. And we implemented the synchronization system that satisfies the specification demanded by the proposed EIA/TIA Interim Standard of Qualcomm Company. We showed that the state of the PN spreading code was estimated using the DMF(Digital Matched Filter) and then exact and fast chip synchronization could be achieved by the early-late tracking loop in the multiple channel environment. And we suggested the possibility that this synchronization system could be useful in the emerging digital cellular DS/CDMA system.

• Journal of Communications and Networks
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• v.9 no.1
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• pp.75-83
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• 2007

Orthogonal frequency division multiplexing (OFDM) systems with multiple transmit antennas can exploit space-time block coding on each subchannel for reliable data transmission. Spacetime coded OFDM systems, however, are very sensitive to time variant channels because the channels need to be static over multiple OFDM symbol periods. In this paper, we propose to mitigate the channel variations in the frequency domain using a linear filter in the frequency domain that exploits the sparse structure of the system matrix in the frequency domain. Our approach has reduced complexity compared with alternative approaches based on time domain block-linear filters. Simulation results demonstrate that our proposed frequency domain block-linear filter reduces computational complexity by more than a factor of ten at the cost of small performance degradation, compared with a time domain block-linear filter.

• Korean Journal of Fisheries and Aquatic Sciences
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• v.36 no.2
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• pp.170-177
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• 2003

This study is to analyze the influence of the Tsushima Warm Current (TWC) on the variation of sound speed in the southern part of the East Sea. Sound speed is calculated by method of Chen and Millero (1977:, based on the CTD data measured in June of 1996. Sound speed in the central part of the TWC is about $45ms^{-1}$ more fast than that in the other regions without the TWC. Sound speed minimum layer (SML) in the TWC region exists between loom and 341 m, while it exists between 260m and 290m in the non-TWC region. SML distributes along the path of TWC over continental shelf in the coastal waters of Japan.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.261-273
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• 2016

Reconfigurable finite impulse response (FIR) filters whose filter coefficients and filter order change dynamically during run-time play an important role in the software defined radio (SDR) systems, multi-channel filters, and digital up/down converters. However, there are not many reports on such reconfigurable designs which can support dynamic variation of filter order and filter coefficients. The purpose of this paper is to provide an architectural solution for the FIR filters to support run-time variation of the filter order and filter coefficients. First, two straightforward designs, namely, (i) single-MAC based design and (ii) full-parallel design are presented. For large variation of the filter order, two designs based on (iii) folded structure and (iv) fast FIR algorithm are presented. Finally, we propose (v) high throughput design which provides significant advantage in terms of hardware and/or time complexities over the other designs. We compare complexities of all the five structures, and provide the synthesis results for verification.