• ETRI Journal
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• v.31 no.6
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• pp.784-794
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• 2009

We present a full HD (1080p) H.264/AVC High Profile hardware encoder based on fast motion estimation (ME). Most processing cycles are occupied with ME and use external memory access to fetch samples, which degrades the performance of the encoder. A novel approach to fast ME which uses shared multibank memory can solve these problems. The proposed pixel subsampling ME algorithm is suitable for fast motion vector searches for high-quality resolution images. The proposed algorithm achieves an 87.5% reduction of computational complexity compared with the full search algorithm in the JM reference software, while sustaining the video quality without any conspicuous PSNR loss. The usage amount of shared multibank memory between the coarse ME and fine ME blocks is 93.6%, which saves external memory access cycles and speeds up ME. It is feasible to perform the algorithm at a 270 MHz clock speed for 30 frame/s real-time full HD encoding. Its total gate count is 872k, and internal SRAM size is 41.8 kB.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.199-203
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• 2013

In this paper, a fast algorithm of discrete cosine transform-based interpolation filter (DCT-IF) for HEVC (high efficiency video coding) encoder is proposed. DCT-IF filter accounts for around 30% of encoder complexity, according to the computational complexity analysis with the HEVC reference software. In this work, the proposed DCT-IF is optimized by applying frame-level interpolation, SIMD optimization, and task-level parallelization via OpenMP on a developed C-based HEVC encoder. Performance analysis is conducted by measuring speed-up factor of the proposed optimization technique on the developed encoder. The results show that speed-up factors by frame-level interpolation, SIMD, and OpenMP are approximately 38-46, 3.6-4.4, and 3.0-3.7, respectively. In the end, we achieved the speed-up factor of 498.4 with the proposed fast algorithm.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.5
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• pp.285-290
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• 2012

In this paper, we propose a fast encoding algorithm for scalable video encoding without compromising coding performance. Through analysis on multiple motion estimation processes performed at the enhancement layer, we show redundant motion estimations and suggest the condition under which the redundant ones can efficiently be determined without additional memory. Based on the condition, the redundant motion estimation processes are excluded in the proposed algorithm. Simulation results show that the proposed algorithm is faster than the conventional fast encoding method without performance degradation and additional memory.

• Journal of Broadcast Engineering
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• v.15 no.4
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• pp.582-590
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• 2010

he rate-distortion optimization (RDO) method in the H.264/AVC encoder is a technology that improves the coding efficiency, but increases the computational complexity. In this paper, a fast Intra mode decision algorithm using DCT (Discrete Cosine Transform) coefficients distribution is proposed to reduce the H.264 encoder complexity. The proposed method reduces the encoder complexity on average 68.40%, while the coding efficiency is slightly decreased compared with the H.264/AVC encoder.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6C
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• pp.459-470
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• 2008

In this paper, we propose a fast ME (motion estimation) algorithm for MPEG-4 to H.264 Transcoder. Whereas 2 modes ($8{\times}8$, $16{\times}16$) are used for ME in MPEG-4 simple profile, ME using 7 modes is supported for further enhanced coding efficiency in H.264. The transcoding speed is affected dominantly by the computational complexity of encoder part in transcoder, where ME module of H.264 encoder has high complexity due to using 7 modes. In order to increase the speed of transcoding between MPEG-4 and H.264, we use 3 PMVs (predicted motion vectors) and the mode information of MBs (macroblocks) provided from the decoder part of transcoder. Since the proposed 3 PMVs are very close to an optimal motion vector, and we consider only some restricted modes according to the MB information transferred from decoder part, the proposed scheme can speed up the transcoding procedure without loss of image quality. We show experimental results which demonstrate the effectiveness of the proposed algorithm, where performance of our scheme is compared with that of the conventional fast algorithm for H.264.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.1097-1100
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• 1999

Due to the significant computation of full search in motion estimation, extensive research in fast motion estimation algorithms has been carried out. However, most of the algorithms have the degradation in predicted images compared with the full search algorithm. To reduce an amount of significant computation while keeping the same prediction quality of the full search, we propose a fast block-matching algorithm based on gradient magnitude of reference block without any degradation of predicted image. By using Taylor series expansion, we show that the block matching errors between reference block and candidate block are proportional to the gradient magnitude of matching block. With the derived result, we propose fast full search algorithm with adaptively determined scan direction in the block matching. Experimentally, our proposed algorithm is very efficient in terms of computational speedup and has the smallest computation among all the conventional full search algorithms. Therefore, our algorithm is useful in VLSI implementation of video encoder requiring real-time application.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.75-82
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• 2004

The channel transmission ratio is speeded up by the combination of the Huffman algorithm, the model scheme of the lossy transform having minimum average code lengths for the image information and good instantaneous decoding capability, with the Lempel-Ziv algorithm showing the fast processing performance during the compression process. In order to increase the processing speed during the compression process, ICMEP algorithm is proposed and the entropy encoder of HDTV is designed and inspected. The ICMEP entropy encoder have been designed by choosing the top-down method and consisted of the source codes and the test benches by the behavior expression with VHDL. As a simulation results, implemented ICMEP entropy encoder confirmed that whole system efficiency by memory saturation prevention and compressibility increase improves.

• Journal of Korea Multimedia Society
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• v.14 no.7
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• pp.849-857
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• 2011

Gaming on demand(GOD) makes people enjoy games by encoding and transmitting game screen at a server side, and decoding the video at a client side. In this paper, we propose a fast game video encoder for multiple users over network with low-powered devices. In the proposed system, the computational complexity of game encoders is reduced by using scene descriptors, which consists of an object motion vector, global motion, and scene change. With additional information from game engines, the proposed encoder does not need to perform various complexity processes such as motion estimation and ratedistortion optimization. The motion estimation and rate-distortion optimization skipped by scene descriptors. We found that the proposed method improved 192 % in terms of FPS, compared with x264 software. With partial assembly code, we also improved coding speed by 86 % in terms of FPS. We found that the proposed fast encoder could encode over 60 FPS for real-time GOD applications.

• Journal of Broadcast Engineering
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• v.20 no.1
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• pp.171-182
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• 2015

HEVC can increase the coding efficiency significantly compared with H.264/AVC however it requires much larger computational complexities in both encoder and decoder. In this paper, the decision process of inter-prediction modes in the HEVC reference software has been studied and a fast algorithm to reduce the computational complexity of encoder and decoder is introduced. The proposed scheme introduces a early decision criteria using the outputs of uni-directional predictions to skip the bi-directional prediction estimation. From the experimental results, it was proven that the proposed method can reduce the encoding complexity by 12.0%, 14.6% and 17.2% with 0.6%, 1.0% and 1.5% of coding efficiency penalty, respectively. In addition, the ratio of bi-directional prediction mode was reduced by 6.3%, 11.8% and 16.6% at the same level of coding efficiency penalty, respectively, which should lead to the decoder complexity reduction. Finally, the effects of the proposed scheme are maintained regardless of the use of the early skip decision algorithm which is implemented in the HEVC reference software.

• Journal of Electrical Engineering and Technology
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• v.3 no.3
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• pp.430-435
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• 2008

In the paper, an algorithm called a Constraint algorithm is proposed to solve the fan-in problem occurred in ADC encoding circuits. The Flash ADC architecture uses a double-base number system (DBNS). The DBNS has known to represent the multi-dimensional logarithmic number system (MDLNS) used for implementing the multiplier accumulator architecture of FIR filter in digital signal processing (DSP) applications. The authors use the DBNS with the base 2 and 3 to represent binary output of ADC. A symmetric map is analyzed first, and then asymmetric map is followed to provide addition read DBNS to DSP circuitry. The simulation results are shown for the Double-Base Integer Encoder (DBIE) of the 6-bit ADC to demonstrate an effectiveness of the Constraint algorithm, using $0.18{\mu}\;m$ CMOS technology. The DBIE’s processing speed of the ADC is fast compared to the FAT tree encoder circuit by 0.95 GHz.