• Proceedings of the Korea Multimedia Society Conference
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• 2012.05a
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• pp.343-344
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• 2012

With the increase of sensitive data and their secure transmission and storage, the use of encryption techniques has become widespread. The performance of encoding majorly depends on the computational time, so a system with less computational time suits more appropriate as compared to its contrary part. Double Random Phase Encoding (DRPE) is an algorithm with many sub functions which consumes more time when executed serially; the computation time can be significantly reduced by implementing important functions in a parallel fashion on Graphics Processing Unit (GPU). Computing convolution using Fast Fourier transform in DRPE is the most important part of the algorithm and it is shown in the paper that by performing this portion in GPU reduced the execution time of the process by substantial amount and can be compared with MATALB for performance analysis. NVIDIA graphic card GeForce 310 is used with CUDA C as a programming language.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.587-591
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• 2004

This paper proposes a novel current compensation technique that can eliminate the harmonic currents included in line currents without computation of harmonic current components. A current controller with fast dynamics for an active filter is described. Harmonic currents are directly controlled without the need for sensing and computing the harmonic current of the load current, thus simplifying the control system. Current compensation is done in the time domain, allowing a fast time response. The DC voltage control loop keeps the voltage across the DC capacitor constant. High power factor control by an active filter is described. All control functions are implemented in software using a single-chip microcontroller, thus simplifying the control circuit. Any current-controlled synchronous rectifier can be used as a shunt active filter through only the simple modification of the software and the addition of current sensors. It is shown through experimental results that the proposed controller gives good performance for the shunt active filter.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.4
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• pp.63-67
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• 2004

The conventional typical techniques as fast codebook generation methods are PDS, FNNS, and FC. In this paper, we propose FCNNPDS integrated the conventional methods to generate a codebook. The results of simulations show that the computational magnitude of FCNNPDS is reduced to 40-95% lower than conventional techniques. But comparison computation has no relation with k dimension of vectors, that is, because the computational magnitude of comparison is smaller than others, therefore FCNNPDS may be the best method than the conventional methods.

• Journal of Information Technology Applications and Management
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• v.23 no.3
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• pp.87-97
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• 2016

This paper proposes a fast sound source localization method using a TDOA sign-based algorithm. We present an L-shaped microphone set-up which creates four major regions in the range of $0^{\circ}{\sim}360^{\circ}$ by the intersection of the positive and negative regions of the individual microphone pairs. Then, we make an initial source region prediction based on the signs of two TDOA estimates before computing the azimuth value. Also, we apply a threshold and angle comparison to tackle the existing front-back confusion problem. Our experimental results show that the proposed method is comparable in accuracy to previous three microphone array methods; however, it takes a shorter computation time because we compute only two TDOA values.

• Journal of information and communication convergence engineering
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• v.8 no.3
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• pp.267-272
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• 2010

For the last decade, recurrent neural networks (RNNs) have been commonly applied to communications channel equalization. The major problems of gradient-based learning techniques, employed to train recurrent neural networks are slow convergence rates and long training sequences. In high-speed communications system, short training symbols and fast convergence speed are essentially required. In this paper, the derivative-free Kalman filter, so called the unscented Kalman filter (UKF), for training a fully connected RNN is presented in a state-space formulation of the system. The main features of the proposed recurrent neural equalizer are fast convergence speed and good performance using relatively short training symbols without the derivative computation. Through experiments of nonlinear channel equalization, the performance of the RNN with a derivative-free Kalman filter is evaluated.

• Proceedings of the KIEE Conference
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• 1989.07a
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• pp.138-141
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• 1989

In resent years, aided by the power and capability of digital computation, the techniques of Walsh Transform have been exploited for applications in commun- ication and signal processing. This paper presents an approach of FWT by using a 16- bit word-length micro- computer. This FWT implements an in-placed decimation-in-sequency algorithm which improves processing speed and memory storage. Several examples illustrate the process and demonstrate the power spectrum of FWT and that of FFT for the waveforms

• Proceedings of the KIEE Conference
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• 2004.07d
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• pp.2350-2352
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• 2004

This paper presents the implementation-tation of the real-time software GPS Receiver based on FFT and FLL assisted PLL tracking algorithm. The FFT(fast fourier transform) based GPS si-gnal acquisition scheme provides a fast TTFF(time to first fix) performance. The tracking based on FLL assisted PLL enables tracking of GPS signal in a high dynamic environment. The designed software GPS receiver uses the indexing method for generating replica carrier to reduce computation load. The performance of the implemented GPS receiver is evaluated using high-dynamic simulated data from a simulator and real static data.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.2 no.1
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• pp.38-42
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• 2002

A fast iterative solving method of fuzzy relational equation is proposed. It is derived by eliminating a redundant comparison process in the conventional iterative solving method (Pedrycz, 1983). The proposed method is applied to image reconstruction, and confirmed that the computation time is decreased to 1 / 40 with the compression rate of 0.0625. Furthermore, in order to make any initial solution converge on a reconstructed image with a good quality, a new cost function is proposed. Under the condition that the compression rate is 0.0625, it is confirmed that the root mean square error of the proposed method decreases to 27.34% and 86.27% compared with those of the conventional iterative method and a non iterative image reconstruction method, respectively.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.904-907
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• 2002

In this paper, we describe an algorithm to automatically generate an intermediate scene using the bidirectional disparity morphing from the parallel stereopair. To compute the disparity between two reference images, we use the 2-step fast block matching algorithm that restricts the searching range and accelerates the speed of the computation of the disparity. We also define three occluding patterns so as to smooth the computed disparities, especially for occluded regions. They are derived from the peculiar properties of the disparity map. The smoothed disparity maps present that the false disparities are well corrected and the boundary between foreground and background becomes sharper. We discuss the advantages of this algorithm compared to the commonly used schemes and we show some experimental results with real data.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.1
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• pp.234-243
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• 1995

An arry circuit is designed for parallel computation of vector-radix 2-D discrete cosine transform (VR-FCT) which is a fast algorithm of DCT. By using a 2-D array of processing elements (PEs), the butterfly structure of the VR-FCT can be efficiently implemented with high condurrency and local communication geometry. The proposed implementation features architectural medularity, regularity and locality, so that it is very suitable for VLSI realization. Also, no transposition memory is required. The array core for (8$\times$8) 2-D DCT, which is designed usign ISRC 1.5.mu.m N-Well CMOS technology, consists of 64 PEs arranged in (8$\times$8) 2-D array and contains about 98,000 transistors on an area of 138mm$^{2}$. From simulation results, it is estimated that (8$\times$8) 2-D DCT can be computed in about 0.88 .mu.sec at 50 MHz clock frequency, resulting in the throughput rate of about 72${\times}10^[6}$ pixels per second.