• Title/Summary/Keyword: Fabrication Process

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The Study of the Fabrication of the Ultra-Precision Cylinder by the Compensation Process (보정 가공을 통한 초정밀 원통 가공에 대한 연구)

  • Lee, Jung-Chul
    • Journal of the Korean Society of Manufacturing Process Engineers
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    • v.12 no.5
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    • pp.122-128
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    • 2013
  • This paper describes the on-machine surface form evaluation of an ultra-precision cylinder for the fabrication by the compensation process. In this study, the surface form error of an ultra-precision cylinder, which was fabricated by the ultra-precision diamond turning machine with a single diamond cutting tool, was evaluated by using two capacitance-type displacement probes. Based on the measurement results, the compensation process was conducted. Since the measurement was carried out on the machine without re-mounting of the workpiece, additional fabrication for compensation process can be conducted precisely.

An Efficient H.264/AVC Entropy Decoder Design (효율적인 H.264/AVC 엔트로피 복호기 설계)

  • Moon, Jeon-Hak;Lee, Seong-Soo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.12
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    • pp.102-107
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    • 2007
  • This paper proposes a H.264/AVC entropy decoder without embedded processor nor memory fabrication process. Many researches on H.264/AVC entropy decoders require ROM or RAM fabrication process, which is difficult to be implemented in general digital logic fabrication process. Furthermore, many researches require embedded processors for bitstream manipulation, which increases area and power consumption. This papers proposes hardwired H.264/AVC entropy decoder without embedded processor, which improves data processing speed and reduces power consumption. Furthermore, its CAVLC decoder optimizes lookup table and internal buffer without embedded memory, which reduces hardware size and can be implemented in general digital logic fabrication process without ROM or RAM fabrication process. Designed entropy decoder was embedded in H.264/AVC video decoder, and it was verified to operate correctly in the system. Synthesized in TSMC 90nm fabrication process, its maximum operation frequency is 125MHz. It supports QCIF, CIF, and QVGA image format. Under slight modification of nC register and other blocks, it also support VGA image format.

Development of Large-area Two-photon Stereolithography Process for the Fabrication of Large Three-dimensional Microstructures (대면적 3 차원 마이크로 형상제작을 위한 스테이지 스캐닝 시스템을 이용한 이광자 흡수 광조형 공정 개발)

  • Lim, Tae-Woo;Son, Yong;Yi, Shin-Wook;Kong, Hong-Jin;Park, Sang-Hu;Yang, Dong-Yol
    • Journal of the Korean Society for Precision Engineering
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    • v.25 no.1
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    • pp.122-129
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    • 2008
  • Two-photon stereolithography is recognized as a promising process for the fabrication of three-dimensional (3D) microstructures with 100 nm resolution. Generally, beam-scanning system has been used in the conventional process of two-photon stereolithography, which is limited to the fabrication of micro-prototypes in small area of several tens micrometers. For the applications to 3D high-functional micro-devices, the fabrication area of the process is required to be enlarged. In this paper, large-area two-photon stereolithography (L-TPS) employing stage scanning system has been developed. Continuous scanning method is suggested to improve the fabrication speed and parameter study is conducted. An objective lens of high numerical aperture (N.A.) and high strength material were employed in this system. Through this work, 3D microstructures of $600*600*100\;{\mu}m$ were fabricated.

Fabrication of Nanoscale Reusable Quartz Master for Nano Injection Molding Process (재사용 가능한 100nm급 패턴의 퀄츠 마스터 제작 및 퀄츠 마스터를 사용한 사출성형실험)

  • Choi Doo-Sun;Lee Joon-Hyoung;Yoo Yeong-Eun;Je Tae-Jin;Whang Kyung-Hyun;Seo Young Ho
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.29 no.2 s.233
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    • pp.228-231
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    • 2005
  • In this paper, we present reusable quartz master fabricated by electron-beam lithography and dry etching process of quartz, and results of injection molding based on the reusable quartz master for the manufacturing of nano-scale information media. Since patterned structures of photoresist can be easily damaged by separation (demolding) process of nickel stamper and master, a master with photoresist cannot be reused in stamper fabrication process. In this work, we have made it possible of the repeated use of master by directly patterning on quart in nickel stamper fabrication process. We have designed and fabricated four different specimens including 100nm, 140nm 200nm and 400nm pit patterns. In addition, both intaglio and embossed carving patterns are fabricated for each specimen. In the preliminary test of injection molding, we have fabricated polycarbonate patterns with varying mold temperature. We have experimentally verified the fabrication process of the reusable quart master and possibility of quartz master as direct stamper.

An Algorithm on Determination of Process Parameters for Roller Bending of Curved Shell Plates (선체 곡판의 롤 굽힘 공정 변수 결정을 위한 가공 형상의 최적 근사 알고리즘)

  • Ryu, Cheol-Ho;Lee, Jang-Hyun;Yoon, Jong-Sung
    • Journal of the Society of Naval Architects of Korea
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    • v.44 no.5
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    • pp.517-525
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    • 2007
  • This paper presents how to approximate an optimal shape of roll bending process in the fabrication of a curved shell plate. The roll bending process usually makes the cylindrical or conic shape from an initial flat plate. It means that the final shape is developable or its surface representation has zero Gaussian curvature. The fabrication shape is important in order to find process parameters of roil bending. An optimal concept is used to determine the developable fabrication shape which is in the closest proximity to the design surface or the given shell plate and is subject to developability. The results and the efficiency of this algorithm are evaluated by applying to some shell plates. Furthermore, the fabrication shape will be fundamental information for other process parameters of roll bending such as the vertical displacement of the center roller and the rolling directions.

Optically Controlled Silicon MESFET Fabrication and Characterizations for Optical Modulator/Demodulator

  • Chattopadhyay, S.N.;Overton, C.B.;Vetter, S.;Azadeh, M.;Olson, B.H.;Naga, N. El
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.10 no.3
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    • pp.213-224
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    • 2010
  • An optically controlled silicon MESFET (OPFET) was fabricated by diffusion process to enhance the quantum efficiency, which is the most important optoelectronic device performance usually affected by ion implantation process due to large number of process induced defects. The desired impurity distribution profile and the junction depth were obtained solely with diffusion, and etching processes monitored by atomic force microscope, spreading resistance profiling and C-V measurements. With this approach fabrication induced defects are reduced, leading to significantly improved performance. The fabricated OPFET devices showed proper I-V characteristics with desired pinch-off voltage and threshold voltage for normally-on devices. The peak photoresponsivity was obtained at 620 nm wavelength and the extracted external quantum efficiency from the photoresponse plot was found to be approximately 87.9%. This result is evidence of enhancement of device quantum efficiency fabricated by the diffusion process. It also supports the fact that the diffusion process is an extremely suitable process for fabrication of high performance optoelectronic devices. The maximum gain of OPFET at optical modulated signal was obtained at the frequency of 1 MHz with rise time and fall time approximately of 480 nS. The extracted transconductance shows the possible potential of device speed performance improvements for shorter gate length. The results support the use of a diffusion process for fabrication of high performance optoelectronic devices.

Design and Fabrication of Super Junction MOSFET Based on Trench Filling and Bottom Implantation Process

  • Jung, Eun Sik;Kyoung, Sin Su;Kang, Ey Goo
    • Journal of Electrical Engineering and Technology
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    • v.9 no.3
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    • pp.964-969
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    • 2014
  • In Super Junction MOSFET, Charge Balance is the most important issue of the trench filling Super Junction fabrication process. In order to achieve the best electrical characteristics, the N type and P type drift regions must be fully depleted when the drain bias approaches the breakdown voltage, called Charge Balance Condition. In this paper, two methods from the fabrication process were used at the Charge Balance condition: Trench angle decreasing process and Bottom implantation process. A lower on-resistance could be achieved using a lower trench angle. And a higher breakdown voltage could be achieved using the bottom implantation process. The electrical characteristics of manufactured discrete device chips are compared with those of the devices which are designed of TCAD simulation.

Evaluation of Microstructure and Mechanical Properties in 17-4PH Stainless Steels Fabricated by PBF and DED Processes (PBF와 DED 공정으로 제조된 17-4PH 스테인리스 강의 미세조직 및 기계적 특성 평가)

  • Yoon, Jong-Cheon;Lee, Min-Gyu;Choi, Chang-Young;Kim, Dong-Hyuk;Jeong, Myeong-Sik;Choi, Yong-Jin;Kim, Da-Hye
    • Journal of the Korean Society of Manufacturing Process Engineers
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    • v.17 no.2
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    • pp.83-88
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    • 2018
  • Additive manufacturing (AM) technologies have attracted wide attention as key technologies for the next industrial revolution. Among AM technologies using various materials, powder bed fusion (PBF) processes and direct energy deposition (DED) are representative of the metal 3-D printing process. Both of these processes have a common feature that the laser is used as a heat source to fabricate the 3-D shape through melting of the metal powder and solidification. However, the material properties of the deposited metals differ when produced by different process conditions and methods. 17-4 precipitation-hardening stainless steel (17-4PH SS) is widely used in the field of aircraft, chemical, and nuclear industries because of its good mechanical properties and excellent corrosion resistance. In this study, we investigated the differences in microstructure and mechanical properties of deposited 17-4PH SS by PBF and DED processes, including the heat treatment effect.

Performance Analysis of Scheduling Rules in Semiconductor Wafer Fabrication (반도체 웨이퍼 제조공정에서의 스케줄링 규칙들의 성능 분석)

  • 정봉주
    • Journal of the Korea Society for Simulation
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    • v.8 no.3
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    • pp.49-66
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    • 1999
  • Semiconductor wafer fabrication is known to be one of the most complex manufacturing processes due to process intricacy, random yields, product diversity, and rapid changing technologies. In this study we are concerned with the impact of lot release and dispatching policies on the performance of semiconductor wafer fabrication facilities. We consider several semiconductor wafer fabrication environments according to the machine failure types such as no failure, normal MTBF, bottleneck with low MTBF, high randomness, and high MTBF cases. Lot release rules to be considered are Deterministic, Poisson process, WR(Workload Regulation), SA(Starvation Avoidance), and Multi-SA. These rules are combined with several dispatching rules such as FIFO (First In First Out), SRPT (Shortest Remaining Processing Time), and NING/M(smallest Number In Next Queue per Machine). We applied the combined policies to each of semiconductor wafer fabrication environments. These policies are assessed in terms of throughput and flow time. Basically Weins fabrication setup was used to make the simulation models. The simulation parameters were obtained through the preliminary simulation experiments. The key results throughout the simulation experiments is that Multi-SA and SA are the most robust rules, which give mostly good performance for any wafer fabrication environments when used with any dispatching rules. The more important result is that for each of wafer fabrication environments there exist the best and worst choices of lot release and dispatching policies. For example, the Poisson release rule results in the least throughput and largest flow time without regard to failure types and dispatching rules.

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Fabrication of Micro/Nano-patterns using MC-SPL(Mechano-Chemical Scanning Probe Lithography) Process

  • Sung, In-Ha;Kim, Dae-Eun
    • International Journal of Precision Engineering and Manufacturing
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    • v.4 no.5
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    • pp.22-26
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    • 2003
  • In this work, a new non-photolithographic micro-fabrication technique is presented. The motivation of this work is to overcome the demerits of the most commonly used photolithographic techniques. The micro-fabrication technique presented in this work is a two-step process which consists of mechanical scribing followed by chemical etching. This method has many advantages over other micro-fabrication techniques since it is simple, cost-effective, rapid, and flexible. Also, the technique can be used to obtain a metal structure which has sub-micrometer width patterns. In this paper, the concept of this method and its application to microsystem technology are described.