• IEMEK Journal of Embedded Systems and Applications
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• v.8 no.1
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• pp.25-29
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• 2013

Recently ARM processor's processing power has been increasing rapidly as it has been applied to consumer electronics products. Because of its computing power and low power consumption, it is used to various embedded systems.( including vision processing systems.) Embedded linux that provides well-made platform and GUI is also a powerful tool for ARM based embedded systems. So short period to develop is one of major advantages to the ARM based embedded system. However, for real-time date processing applications such as an image processing system, ARM needs additional equipments such as FPGA that is suitable to parallel processing applications. In this paper, we developed an embedded system using ARM processor and FPGA. FPGA takes time consuming image preprocessing and numerical algorithms needs floating point arithmetic and user interface are implemented using the ARM processor. Overall processing speed of the system is 60 frames/sec of VGA images.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04a
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• pp.934-936
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• 2004

본 논문의 목적은 AES(Advanced Encryption Standard)로 선정된 Rijndael 암호 및 복호 알고리즘을 하드웨어로 설계하고 이를 저비용의 FPGA로 구현하는 것이다. 설계된 AES 암호프로세서는 20만 게이트 급 이하의 FPGA로 구현한다는 비용의 제약 조건 하에서 대용량의 데이터를 암호화, 복호화 하기에 적합한 성능을 가지도록 하였다. 또한 구현 단계에서는 설계한 AES 암호프로세서와 UART 모듈을 동일 FPGA상에서 통합하여 실용성 및 면적 효율성을 보였다. 구현된 Rijndael 암호 프로세서는 20만 게이트를 갖는 Xilinx사의 Spartan-II 계열의 XC2S200 칩 사용시 53%의 면적을 차지하였고, Static Timing Analyzer로 분석한 결과 최대 29.3MHz 클럭에서 동작할 수 있고 337Mbps의 최대 성능을 가진다. 구현된 회로는 실제 FPGA를 이용하여 검증을 수행하였다.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.1
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• pp.106-111
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• 2007

In this study, we designed a digital fuzzy logic controller based on FPGA and microprocessor for MPPT of the sofar power generation system. A fuzzy algorithm to control the power tracking function of a boost converter has been built into the FPGA, and applied to the small scaled solar power generation system. The embodied controller showed a stable operation characteristic with the small output voltage ripple for the intensity change of solar radiation. This result proves that the implementation of the power tracking controller using FPGA is an effective way compared to the existing one using microprocessor.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.274-277
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• 1999

The paper describes a implementation of space vector pulse-width modulation (SVPWM) voltage source inverter using Field Programmable Gate Array(FPGA) for a induction motor control system. The implemented chip is included logic circuits for SVPWM, dead time compensation and speed detection using Quick Logic, QL16X24B. The maximum operating frequency and delay time can be set to 110MHz and 6 nsec. The designed FPGA for SVPWM can be incorporated with a digital signal processing to provide a simple and effective solution for high performance voltage source inverter drives. Simulation and Implementation results are shown to verify the usefulness of FPGA as a Application Specific Integrated Circuit(ASIC) in power electronics applications

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.1787-1790
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• 2003

In this paper. we proposed a hardware(H/W) structure which can compress the video and embed the watermark in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into H/W with the efficient structure for FPGA. The global operations of the designed H/W consists of the image compression with the watermarking and the reconstruction, and the watermarking operation is concurrently operated with the image compression. The implemented H/W used the 59％(12943) LAB(Logic Array Block) and 9％(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70㎒ clock frequency over. So we verified the real time operation, 60 fields/sec(30 frames/sec).

• Journal of the Korea Society of Computer and Information
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• v.21 no.11
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• pp.39-47
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• 2016

In this paper, we propose an approach for real time computation of rayleigh CLAHE using a FPGA. The contrast enhancement technique should be applied in thermal equipment having a low contrast image. And thermal equipment must be processed in real time. The CLAHE is an improved algorithm based Histogram Equalization, but the HW design is complex. A value greater than a given threshold in CLAHE should be equally distributed on the other histogram bin, this process requires iterations for the distribution. But implementation of this processing in the FPGA is constrained, so this section was implemented on the assumption of the histogram distribution or modified the operation process or implemented separately in the CPU. In this paper, we designed a distinct redistribution operation in two stages. So FPGA was designed for easy, this was designed to be distributed evenly without the assumptions and constraints. In addition, we have designed a CLAHE with the rayleigh distribution to the FPGA. The simulation shows that the proposed method provides a better image quality in the thermal image.

• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2112-2114
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• 2003

In this paper, We used FPGA which was high speed counter implementation. It was Counting accurately rather fast so that there were we as a counter facility of the pulse implemented. We constructed wide environment rather because we used H8/3672 with FPGA. This FPGA was sythesized by A54SX72A. FPGA programmed by VHDL for a 208pin PQFP package. The measurement the pulse is possible though it peels off a maximum 200kHz. There is used at a stopping action movement and control of the body.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.5
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• pp.906-911
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• 2008

This paper designed Simulik Model to cancel the carrier frequency offset in OFDM using CORDIC Algorithm and evaluated its performance. And Simulink Model compared with Xilinx System Generator Model for FPGA implementation. As a result of simulation, we confirmed that both model is error free by CORDIC when offset frequency is lower than $10^5MHz$. Also, we verified the performance through Hardware Co-simulation with Xilinx Spartan3 xc3s1000 fg676-4 Target Device, and timing analysis and resource estimation.

• Journal of the Korean Society of Systems Engineering
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• v.14 no.2
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• pp.49-57
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• 2018

The main objective of this paper is come up with methodology approach for FPGA-based system in verification and validation lifecycle regarding software reliability using system engineering approach. The steps of both reverse engineering and re-engineering are carried out to implement an FPGA-based of safety critical system in Nuclear Power Plant. The reverse engineering methodology is applied to elicit the requirements of the system as well as gain understanding of the current life cycle and V&V activities of FPGA based-system. The re-engineering method is carried out to get a new methodology approach of software reliability, particularly Software Reliability Growth Model. For measure the software reliability of a given FPGA-based system, the following steps are executed as; requirements definition and measurement, evaluation of candidate reliability model, and the validation of the selected system. As conclusion, a new methodology approach for software reliability measurement using software reliability growth model is developed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.485-488
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• 2009

The class of BCH codes is a large class of error correction codes. HDL implementation of BCH code generator to change code rate. and used System Generator, and implemented hardware to FPGA. Loaded bit stream to a FPGA board in order to verify this design to Hardware co-simulation from these results. Also, compared as investigated the maximum action frequency through timing analysis and resource of logic in order to evaluate performance of BCH code generator.