• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2000년도 전력전자학술대회 논문집
• /
• pp.61-65
• /
• 2000

In this paper We have developed the high-speed controller for haptic control. The proposed controller is based on the PCI/FPGA technology which can calculate the real position and transmit the force data to device rapidly. The haptic system is composed of 6DOF force display device high-speed controller. The developed system will be used on constructing the dynamical virtual environment. To show the efficiency of our system we designed simulation program of force-reflecting. As the result of the experiment we found that the controller has much higher resolution than some other controller It is so efficient in a 1 PC-based system with 1[kHz] haptic interrupt cycle.

• Journal of Electrical Engineering and Technology
• /
• 제10권4호
• /
• pp.1655-1666
• /
• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• 항공우주시스템공학회지
• /
• 제11권1호
• /
• pp.41-46
• /
• 2017

소형 다중로터 드론의 동작 실험을 위하여 개발한 장치를 소개한다. 개발한 장치는, 볼 부슁 메카니즘, 이동형 지지대, 그리고 회전판을 적용하여 6자유도 운동이 가능하다. 병렬 처리가 가능한 FPGA기반의 제어기를 사용하여, 가속도와 자이로 센서로 부터 자세를 측정하고 모터 속도를 제어하였다. 다양한 동작을 수행하면서 실험 장치와 제어기의 동작성을 확인하였다. 결론적으로, 개발한 6자유도 실험 장치는 소형 드론 제어를 위한 제어기의 성능 검증을 위해 적합하다.

• 한국마린엔지니어링학회:학술대회논문집
• /
• 한국마린엔지니어링학회 2006년도 전기학술대회논문집
• /
• pp.249-250
• /
• 2006

In this paper, hardware design and implementation of digital controller for the High Precision Digital Power Supply (HPDPS) based on Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA) is presented. Developed digital controller is composed of high resolution Digital Pulse Width Modulation (DPWM) and high resolution analog to digital converter circuit with anti-aliasing filter. And Digital Signal Processor (DSP) has the capability of a few micro-second calculation time for one feedback loop. 32-bit DSP and DPWM with 150[ps] step resolution is used to implement the HPDPS. Also 18-bit 2 mega sample per second ADC board is adopted for the developed digital controller. Also, hardware structure of the developed digital controller and experimental results of the first prototype board for HPDPS is described.

• Advances in Energy Research
• /
• 제1권2호
• /
• pp.97-106
• /
• 2013

This study designs and tests a photovoltaic system with distributed maximum power point tracking (DMPPT) methodology using a field programmable gate array (FPGA) controller. Each solar panel in the distributed PV system is equipped with a newly designed DC/DC converter and the panel's voltage output is regulated by a FPGA controller using PI control. Power from each solar panel on the system is optimized by another controller where the quadratic maximization MPPT algorithm is used to ensure the panel's output power is always maximized. Experiments are carried out at atmospheric insolation with partial shading conditions using 4 amorphous silicon thin film solar panels of 2 different grades fabricated by Chi-Mei Energy. It is found that distributed MPPT requires only 100ms to find the maximum power point of the system. Compared with the traditional centralized PV (CPV) system, the distributed PV (DPV) system harvests more than 4% of solar energy in atmospheric weather condition, and 22% in average under 19% partial shading of one solar panel in the system. Test results for a 1.84 kW rated system composed by 8 poly-Si PV panels using another DC/DC converter design also confirm that the proposed system can be easily implemented into a larger PV power system. Additionally, the use of NI sbRIO-9642 FPGA-based controller is capable of controlling over 16 sets of PV modules, and a number of controllers can cooperate via the network if needed.

• 제어로봇시스템학회:학술대회논문집
• /
• 제어로봇시스템학회 2004년도 ICCAS
• /
• pp.1254-1258
• /
• 2004

This paper presents of position control of Permanent Magnet Synchronous Motor (PMSM) the implementation with Field Programmable Gate Array (FPGA) is proposed. Cascade control with inner loop as a current control and an outer loop as a position control is chosen for simplicity and fast response. FPGA is a single chip (single processing unit), which will perform the following tasks: receive and convert control signal, create a reference current signal, control current and create switch signal and act as position controller in a addition of zero form. The 10 kHz sampling frequency and 25 bit of floating point data are defined in this implementation.The experimental results show that the performance of FPGA based position control is comparable with the hardware based position control, with the advantage of control algorithm flexibility

• 제어로봇시스템학회논문지
• /
• 제13권10호
• /
• pp.970-977
• /
• 2007

Absolute position detector which is one of the major equipment in the field of factory automation, not only perceives the absolute position of the rotary machine but also outputs switch data according to the given angle. Absolute position detector is composed of sensor module and its controller. In this paper, a sensor driver is implemented using FPGA with VHDL. This chip has a less form factor than conventional circuit. A test shows reliable precision within THD(total harmonic distortion) of 0.2% which can be applicable commercially. Also, FPGA-based phase error compensation methods were newly discussed. In the future, more research will be conducted to enhance the precision by the introduction of 3-phase transformer.

• 전기전자학회논문지
• /
• 제20권3호
• /
• pp.333-336
• /
• 2016

차량 내 전자장치에서 효과적인 서브 버스로서 표준화된 저속 직렬 통신 프로토콜인 LIN(local interconnect network)이 개발되었다. 본 논문에서는 LIN 버전 2.2A를 기반으로 LIN 제어기를 Verilog HDL을 이용하여 구현하였다. 구현된 LIN 제어기는 FPGA에서 동작을 확인하였으며 IP 형태로 제공되어 SoC 시스템에 통합이 가능하다. 0.18um 공정에서 합성하였을 때의 게이트 수는 약 2,300 게이트이다.

• 한국정보통신학회논문지
• /
• 제11권8호
• /
• pp.1424-1433
• /
• 2007

본 논문에서 는 하드웨어의 구현을 위해 수정된 CGH(Computer Generated Hologram) 알고리즘을 바탕으로 디지털 홀로그램을 생성할 수 있는 하드웨어 구조를 제안하고 FPGA(Field Programmable Gate Array)를 기반으로 구현하고자 한다. 먼저 CGH 알고리즘을 분석 한 후에 디지털 홀로그램을 효율적으로 연산할 수 있는 CGH 셀 (cell)의 구조를 제안하고 CGH 셀의 확장을 통해서 CGH 커널 (kernel)을 구현한다. 그리고 최종적으로 CGH 커널과 SDRAM Controller, DMA 등의 블록들을 결합하여 CGH 프로세서를 구현한다. 제안한 구조는 CGH 커널 내 CGH 셀의 단순한 추가를 통해서 성능을 비례적으로 증가시킬 수 있다. 이는 CGH 셀들이 독립적으로 동작하기 때문이다. 제안한 하드웨어는 Xilinx의 XC2VP70 FPGA를 이 용하여 구현하였고 200 MHz의 동작속도에서 40,000개의 광원으로 구성된 3차원 객체를 0.205초에 $1,280{\times}1,024$크기 의 홀로그램으로 생성 할 수 있다.

• Nuclear Engineering and Technology
• /
• 제45권4호
• /
• pp.477-488
• /
• 2013

The PLC (Programmable Logic Controller) has been widely used to implement real-time controllers in nuclear RPSs (Reactor Protection Systems). Increasing complexity and maintenance cost, however, are now demanding more powerful and cost-effective implementation such as FPGA (Field-Programmable Gate Array). Abandoning all experience and knowledge accumulated over the decades and starting an all-new development approach is too risky for such safety-critical systems. This paper proposes an RPS software development process with a platform change from PLC to FPGA, while retaining all outputs from the established development. This paper transforms FBD designs of the PLC-based software development into a behaviorally-equivalent Verilog program, which is a starting point of a typical FPGA-based hardware development. We expect that the proposed software development process can bridge the gap between two software developing approaches with different platforms, such as PLC and FPGA. This paper also demonstrates its effectiveness using an example of a prototype version of a real-world RPS in Korea.