• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.2519-2523
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• 2003

Ultrasonic sensors are widely used in mobile robot applications to recognize external environments, because they are cheap, easy to use, and robust under varying lighting conditions. In most cases, a single ultrasonic sensor is used to measure the distance to an object based on time-of-flight (TOF) information, whereas multiple sensors are used to recognize the shape of an object, such as a corner, plane, or edge. However, the conventional sequential driving technique involves a long measurement time. This problem can be resolved by pulse coding ultrasonic signals, which allows multi-sensors to be fired simultaneously and adjacent objects to be distinguished. Accordingly, the current presents a new simultaneous coded driving system for an ultrasonic sensor array for object recognition in autonomous mobile robots. The proposed system is designed and implemented using a DSP and FPGA. A micro-controller board is made using a DSP, Polaroid 6500 ranging modules are modified for firing the coded signals, and a 5-channel coded signal generating board is made using a FPGA. To verify the proposed method, experiments were conducted in an environment with overlapping signals, and the flight distances for each sensor were obtained from the received overlapping signals using correlations and conversion to a bipolar PCM-NRZ signal.

• The KIPS Transactions:PartA
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• v.14A no.7
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• pp.391-398
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• 2007

In this paper, we design a future mobile camera standard interface based on the MIPI CSI-2 and D-PHY specification. The proposed CSI-2 have the efficient multi-lane management layer, which the independent buffer on the each lane are merged into single buffer. This scheme can flexibly manage data on multi lanes though the number of supported lanes are mismatched in a camera processor transmitter and a host processor. The proposed CSI-2 & D-PHY are verified under test bench. We make an experiment on CSI-2 & D-PHY with FPGA type test-bed and implement them onto a mobile handset. The proposed CSI-2 & D-PHY module are used as both the bridge type and the future camera processor IP for SoC.

• Proceedings of the KIEE Conference
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• 2001.07b
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• pp.1212-1214
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• 2001

In this paper ASIC design technique using VHDL is applied to MRAS based speed sensorless control of induction motor. ASIC for MRAS based speed sensorless control is designed through the description of speed estimator using FSM, stator voltage controller, flux angle detector, coordinate transformation, and inverter switching signal output. Finally the above system has been implemented on the FPGA (VERTEX XCV400HQ240). Simulation and experiment have been performed to verify the performance of the designed ASIC.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.188-198
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• 2013

In order to increase its performance, NAND flash memory-based storage is composed of data buses that are shared by a number of flash memories and uses a parallel technique that can carry out multiple flash memory operations simultaneously. Since the storage performance is strongly influenced by the performance of each data bus, it is important to improve the utilization of the bus by ensuring effective scheduling of operations by the storage controller. However, this is difficult because of dynamic changes in buses due to the unique characteristics of each operation with different timing, cost, and usage by each bus. Furthermore, the scheduling technique for increasing bus utilization may cause unanticipated operation delay and wastage of storage resource. In this study, we suggest various dynamic operation scheduling techniques that consider data bus performance and storage resource efficiency. The proposed techniques divide each operation into three different stages and schedule each stage depending on the characteristics of the operation and the dynamic status of the data bus. We applied the suggested techniques to the controller and verified them on the FPGA platform, and found that program operation decreased by 1.9% in comparison to that achieved by a static scheduling technique, and bus utilization and throughput was approximately 4-7% and 4-19% higher, respectively.

• Proceedings of the KSR Conference
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• 2011.05a
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• pp.1195-1201
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• 2011

Since the release of safety standard IEC 61508 which defines functional safety of electronic safety-related systems, SIL(Safety Integrity Level) certification for railway systems has gained lots of attention lately. In this paper, we propose a new design technique of the computer board for train control systems with high reliability and safety. The board is designed with TMR(Triple Modular Redundancy) using a certified SIL3 Texas Instrument(TI)'s TMS570 MCU(Micro-Controller Unit) to guarantee safety and reliability. TMR for the control device is implemented on FPGA(Field Programmable Gate Array) which integrates a comparator, a CAN(Controller Area Network) communication module, built-in self-error checking, error discriminant function to improve the reliability of the board. Even if a malfunction of a processing module occurs, the safety control function based on the proposed technique lets the system operate properly by detecting and masking the malfunction. An RTOS (Real Time Operation System) called FreeRTOS is ported on the board so that reliable and stable operation and convenient software development can be provided.

• Journal of Power Electronics
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• v.16 no.1
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• pp.190-204
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• 2016

An active front end (AFE) is required for a three-phase induction motor (IM) fed by a voltage source inverter (VSI), because of the increasing need to derive quality current from the utility end without sacrificing the power factor (PF). This study investigates a proportional-plus-integral (PI) controller based AFE topology that uses a super-lift converter (SLC). The significance of the proposed SLC, which converts rectified AC supply to geometrically proceed ripple-free DC supply, is explained. Variations in several power quality parameters in the intended IM drive for 0% and 100% loading conditions are demonstrated. A simulation is conducted by using MATLAB/Simulink software, and a prototype is built with a field programmable gate array (FPGA) Spartan-6 processor. Simulation results are correlated with the experimental results obtained from a 0.5 HP IM drive prototype with speed feedback and a voltage/frequency (V/f) control strategy. The proposed AFE topology using SLC is suitable for three-phase IM drives, considering the supply end PF, the DC-link voltage and current, the total harmonic distortion (THD) in supply current, and the speed response of IM.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.76-84
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• 2009

This paper proposes a SOC platform which is eligible for education and application SOC design. The platform, fully synthesizable and reconfigurable, includes the OpenRISC embedded processor, some basic peripherals such as GPIO, UART, debug interlace, VGA controller and WISHBONE interconnect. The platform uses a set of development environment such as compiler, assembler, debugger and RTOS that is built for HW/SW system debugging and software development. Designed SOC, IPs and Testbenches are described in the Verilog HDL and verified using commercial logic simulator, GNU SW development tool kits and the FPGA. Finally, a multimedia SOC derived from the SOC platform is implemented to ASIC using the Magnachip cell library based on 0.18um 1-poly 6-metal technology.

• Journal of Institute of Control, Robotics and Systems
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• v.15 no.11
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• pp.1096-1101
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• 2009

In this paper, an embedded system has been designed for force control application to interact between a robot arm and a human operator. Force induced by the human operator is converted to the desired position information for the robot to follow. For smooth operations, the impedance force control algorithm is utilized to represent interaction between the robot and the human operator by filtering the force. To improve the performance of position control of the robot arm, a velocity term has been obtained and tested by several filters. A PD controller for position control has been implemented on an FPGA as well. Experimental studies are conducted with the ROBOKER to test the functionality of the designed hardware.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.78-80
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• 2005

The pattern recognition of automobile and parking line for the automatic car parking system was processed based on statistical method for reducing the processing time. The command of driving for parking at the vacant parking lot was transmitted from processor to motor driven actuator using direct sequence spread spectrum communication, which enables the multiple transmission in CAN(controller area network). The test-bed which has CCD camera, processor, radio transceiver and FPGA was implemented and demonstrated to be operated well.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.111.3-111
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• 2001

Automative system and robot are operated by motor. Recently, automative system and robot need correct operation and control for precise task. Therefore they need precise motor control technology. In present, controller needs precise motor control technology in automative system and robot. Usual step motor driver that has 200 steps per revolution is not proper. So we need micro step motor driver that is more precise then usual step motor driver. In this paper, micro step motor driver is used for precise control of step motor. The goal is precise operation and location control. This micro step motor driver is A3972SB that is made in Alloegro Company. It has serial port that receives two 6-bits linear DAC value. Almost all systems generate DAC value with micro processer and ...