• Journal of IKEEE
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• v.22 no.1
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• pp.87-92
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• 2018

Like CPUs, regular expression processors that perform regular expression pattern matching using instructions have been proposed recently. Of these, only REMPc provides features for character class matching. In this paper, we propose an architecture for efficient character class matching in a regular expression processor, which use character class bitmap format in a instruction operand field and implement the hard-wired character class comparator for several frequently used character classes. Using the proposed method, most of the character classes used in Snort rule can be represented by an operand or an instruction. Thus, character class matching can be performed more efficiently in the proposed archiecture than in REMPc.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.777-780
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• 2003

We have tried to create a vision system like human eye for a long time. We have obtained some distinguished results through many studies. Stereo vision is the most similar to human eye among those. This is the process of recreating 3-D spatial information from a pair of 2-D images. In this paper, we have designed a stereo matching algorithm based on systolic array architecture using edges and pixel data. This is more advanced vision system that improves some problems of previous stereo vision systems. This decreases noise and improves matching rate using edges and pixel data and also improves processing speed using high integration one chip FPGA and compact modules. We can apply this to robot vision and automatic control vehicles and artificial satellites.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.4
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• pp.237-250
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• 2015

This paper describes a hardware-oriented algorithm and its conceptual implementation in a real-time speed limit traffic sign detection system on an automotive-oriented field-programmable gate array (FPGA). It solves the training and color dependence problems found in other research, which saw reduced recognition accuracy under unlearned conditions when color has changed. The algorithm is applicable to various platforms, such as color or grayscale cameras, high-resolution (4K) or low-resolution (VGA) cameras, and high-end or low-end FPGAs. It is also robust under various conditions, such as daytime, night time, and on rainy nights, and is adaptable to various countries' speed limit traffic sign systems. The speed limit traffic sign candidates on each grayscale video frame are detected through two simple computational stages using global luminosity and local pixel direction. Pipeline implementation using results-sharing on overlap, application of a RAM-based shift register, and optimization of scan window sizes results in a small but high-performance implementation. The proposed system matches the processing speed requirement for a 60 fps system. The speed limit traffic sign recognition system achieves better than 98% accuracy in detection and recognition, even under difficult conditions such as rainy nights, and is implementable on the low-end, low-cost Xilinx Zynq automotive Z7020 FPGA.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.12
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• pp.2484-2491
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• 2009

This paper proposes robust state feedback control of asynchronous sequential machines with model uncertainty. The considered asynchronous machine is deterministic, but its state transition function is partially known before executing a control process. The main objective is to derive the existence condition for a corrective controller for which the behavior of the closed-loop system can match a prescribed model in spite of uncertain transitions. The proposed control scheme also has learning ability. The controller perceives true state transitions as it undergoes corrective actions and reflects the learned knowledge in the next step. An adaptation is made such that the controller can have the minimum number of state transitions to realize a model matching procedure. To demonstrate control construction and execution, a VHDL and FPGA implementation of the proposed control scheme is presented.

• Proceedings of the IEEK Conference
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• 2002.06d
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• pp.287-290
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• 2002

The block matching algorithm motion estimation is a soft-core for hardwired motion estimation block in MPEG-2, H.261 encoder. This motion estimation has been tested and verified to be valid for implementation of FPGA. Efficiency performance of the synthesized motion estimation was up to 89%, and the average PSNR between the original image and the motion-compensated image is 38dB.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.2
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• pp.102-113
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• 2014

This paper suggests a novel hardware architecture of a real-time rectification which is to remove vertical parallax of an image occurred in the pre-processing stage of stereo matching. As an off-line step, Matlab Toolbox which was designed by J.Y Bouguet, was used to calculate calibration parameter of the image. Then, based on the Heikkila and Silven's algorithm, rectification hardware was designed. At this point, to enhance the precision of the rectified image, floating-point unit was generated by using Xilinx Core Generator. And, we confirmed that proposed hardware design had higher precision compared to other designs while having the ability to do rectification in real-time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.4
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• pp.629-637
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• 2006

Currently the research on input-queued ATM switches is one of the most active research fields. Many achievements have been made in the research on scheduling algorithms for input-queued ATM switches and also applied in commerce. The scheduling algorithms have the characteristics of improving throughput, satisfying QoS requirements and providing service fairly. In this paper, we studied on an implementation of scheduler which arbirates the input-queued ATM switches efficiently and swiftly. The proposed scheduler approximately provides 100% throughput for scheduling. The proposed algorithm completes the arbitration for N-port VOQ switch with 4-iterative matching. Also the proposed algorithm has a merit for implementing the scheduling algorithm with 1/2 area compared to that of iSLIP scheduling algorithm which is widely used. The performance of the proposed scheduling algorithm is superior to that of iSLIP in 4-iterative matching. The proposed scheduling algorithm was implemented in FPGA and verified on board-level.

• Journal of Platform Technology
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• v.6 no.4
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• pp.26-33
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• 2018

In this paper, we propose an image retrieval algorithm for real-time processing and design it as hardware. The proposed method is based on the classification of BoWs(Bag of Words) algorithm and proposes an image search algorithm using bit stream. K-fold cross validation is used for the verification of the algorithm. Data is classified into seven classes, each class has seven images and a total of 49 images are tested. The test has two kinds of accuracy measurement and speed measurement. The accuracy of the image classification was 86.2% for the BoWs algorithm and 83.7% the proposed hardware-accelerated software implementation algorithm, and the BoWs algorithm was 2.5% higher. The image retrieval processing speed of BoWs is 7.89s and our algorithm is 1.55s. Our algorithm is 5.09 times faster than BoWs algorithm. The algorithm is largely divided into software and hardware parts. In the software structure, C-language is used. The Scale Invariant Feature Transform algorithm is used to extract feature points that are invariant to size and rotation from the image. Bit streams are generated from the extracted feature point. In the hardware architecture, the proposed image retrieval algorithm is written in Verilog HDL and designed and verified by FPGA and Design Compiler. The generated bit streams are stored, the clustering step is performed, and a searcher image databases or an input image databases are generated and matched. Using the proposed algorithm, we can improve convenience and satisfaction of the user in terms of speed if we search using database matching method which represents each object.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.12
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• pp.2469-2475
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• 2015

A structured XML has been widely used to present services on various Web-services. The XML is also used for digital documents and digital signatures and for the representation of multimedia files in email systems. The XML document should be firstly parsed to access elements in the XML. The parsing is the most compute-instensive task in the use of XML documents. Most of the previous work has focused on hardware based XML parsers in order to improve parsing performance, while a little work has studied parsing techniques. We present the high performance parsing technique which can be used all of XML parsers and design hardware based XML parser using an FPGA. The proposed parsing technique uses element analyzers instead of the state machine and performs multibyte-based element matching. As a result, our parsing technique can reduce the number of clock cycles per byte(CPB) and does not need to require any preprocessing, such as loading XML data into memory. Compared to other parsers, our parser acheives 1.33~1.82 times improvement in the system performance. Therefore, the proposed parsing technique can process XML documents in real time and is suitable for applying to all of XML parsers.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11B
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• pp.1020-1029
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• 2008

This paper proposes an high speed pattern matching algorithm and its implementation. The pattern matcher is used to check patterns from realtime input packet. The proposed algorithm can find exact string, range of string values, and combination of string values from input packet at high speed. Given string and rule set are modelled as a state transition graph which can find overlapped strings simultaneously, and the state transition graph is partitioned according to input implicants to reduce implementation complexity. The pattern matcher scheme uses the transformed state transition graph and input packet as an input. The pattern matcher was modelled and implemented in VHDL language. Experimental results show the proprieties of the proposed approach.