• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.3
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• pp.173-182
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• 2014

The CRT monitor display system for SONAR signal that are commonly used in ships or naval vessels uses vector scanning method. Therefore the processing circuits of the system are complex. Also the purchase of parts is difficult as well as high-cost because the production had been shut down. FPGA-based embedded system is flexible to various digital applications because it can be able to simplify processing circuits and to make a easy customized design for end user, and it provides low-cost high-speed performance. In this paper, we describe an implementation of FPGA embedded system for real-time SONAR signal display using the triple buffering method to overcome some weakness of existing CRT system. Our system provides real-time acquisition and display capability of SONAR signal, and removes afterimage effect that is a critical problem of the system proposed in the preceding study.

• Journal of Institute of Control, Robotics and Systems
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• v.13 no.12
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• pp.1153-1159
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• 2007

This paper presents the hardware implementation of nonlinear PID controllers for the ROBOKER humanoid robot arms. To design the nonlinear PID controller on an FPGA chip, nonlinear functions as well as the conventional PID control algorithm have to be implemented by the hardware description language. Therefore, nonlinear functions such as trigonometric or exponential functions are designed on an FPGA chip. Simulation studies of the position control of humanoid arms are conducted and results are compared. Superior performances by the nonlinear PID controllers are confirmed when disturbances are present. Experiments of humanoid robot arm control tasks are conducted to confirm the performance of our hardware design and the simulation results.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.12
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• pp.9-19
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• 1997

This paper describes the design and FPGA implementation of a system control unit within a multiprocessor chip which can be used as a node processor ina massively parallel processing (MPP) caches, memory management units, a bus unit and a system control unit. Major functions of the system control unit are locking/unlocking of the shared variables of protected access, synchronization of instruction execution among four integer untis, control of interrupts, generation control of processor's status, etc. The system control unit was modeled in very high level using verilog HDL. Then, it was simulated and verified in an environment where trap handler and external interrupt controller were added. Functional blocks of the system control unit were changed into RTL(register transfer level) model and synthesized using xilinx FPGA cell library in synopsys tool. The synthesized system control unit was implemented by Xilinx FPGA chip (XC4025EPG299) after timing verification.

• Journal of the Semiconductor & Display Technology
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• v.13 no.4
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• pp.71-76
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• 2014

This paper presents the implementation for the BLDC motor speed control system using VHDL and FPGA. The BLDC motor is widely used in automation for its good robustness and easy controllability. In order to control the speed of the BLDC motor, the PI controller used for static RPM output of the BLDC motor to variations in load. In addition, by using the DA converter, we were able to monitor the BLDC motor reference speed and the current speed through real time. The motor speed command and the parameters of the PI speed controller were modified easily by the FPGA and the AD converter. Finally, in order to show the feasibility of the control algorithm the speed control characteristics of the motor was monitored using an oscilloscope and the DA converter. Further, the speed control system was designed in this paper has shown the applicability of the drive system of the factory automation.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.5
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• pp.963-969
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• 2006

In this study, we designed a digital fuzzy logic controller based on FPGA and microprocessor for MPPT of the solar power generation system. A fuzzy algorithm to control the power tracking function of a boost converter has been built into the FPGA, and applied to the small scaled solar power generation system. The embodied controller showed a stable operation characteristic with the small output voltage ripple for the intensity change of solar radiation. This result proves that the implementation of the power tracking controller using FPGA is an effective way compared to the existing one using microprocessors.

• Journal of the Semiconductor & Display Technology
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• v.21 no.4
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• pp.23-26
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• 2022

In this paper, our ray tracing hardware is implemented on the latest high-capacity FPGA board. The system included ray tracing hardware for rendering and tree building hardware for handling dynamic scenes. The FPGA board used in the implementation is a Xilinx Alveo U250 accelerator card for data centers. This included 12 ray tracing hardware cores and 1 tree-building hardware core. As a result of testing in various scenes in Full HD resolution, the FPS performance of the proposed ray tracing system was measured from 8 to 28. The overall average is about 17.7 FPS.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.12
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• pp.1667-1674
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• 2018

Recently, speeding up real time calculation using the specialized hardware accelerator is often used in the various engineering and science area, and the accelerators are required to include PCI express interconnection between FPGA and a host computer. The implementation of the high speed PCIe for the multi-giga bytes per second transmission is one of the most difficult issue in the development of the accelerators. There are several commercialized IP solutions and research results in the literature, but these solutions are required extra cost and design period to analyze the detailed implementation method. For the hardware accelerator on Xilinx FPGA, utilizing Xilinx's XDMA PCIe IP, which is provided without extra charge, can be the best solution in terms of the development period and cost. Consequently, this paper presents the evaluation system on Zynq-7000 FPGA and Windows 10 host computer, and analyze the performance of the PCIe IP with various configuration parameters.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.6
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• pp.717-726
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• 2002

In this study, we analyze hardware implementation schemes of the ARS(Advanced Encryption Standard-128) algorithm that has recently been selected as the standard cypher algorithm by NIST(National Institute of Standards and Technology) . The implementation schemes include the basic architecture, loop unrolling, inner-round pipelining, outer-round pipelining and resource sharing of the S-box. We used MaxPlus2 9.64 for VHDL design and simulations and FLEX10KE-family FPGAs produced by Altera Corp. for implementations. According to the results, the four-stage inner-round pipelining scheme shows the best performance vs. cost ratio, whereas the loop unrolling scheme shows the worst.

• International Journal of Aeronautical and Space Sciences
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• v.17 no.4
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• pp.467-475
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• 2016

Ultrasonic propagation imaging (UPI) has shown great potential for detection of impairments in complex structures and can be used in wide range of non-destructive evaluation and structural health monitoring applications. The software implementation of such algorithms showed a tendency in time-consumption with increment in scan area because the processor shares its resources with a number of programs running at the same time. This issue was addressed by using field programmable gate arrays (FPGA) that is a dedicated processing solution and used for high speed signal processing algorithms. For this purpose, we need an independent and flexible block of logic which can be used with continuously evolvable hardware based on FPGA. In this paper, we developed an FPGA-based ultrasonic propagation imaging system, where FPGA functions for both data acquisition system and real-time ultrasonic signal processing. The developed UPI system using FPGA board provides better cost-effectiveness and resolution than digitizers, and much faster signal processing time than CPU which was tested using basic ultrasonic propagation algorithms such as ultrasonic wave propagation imaging and multi-directional adjacent wave subtraction. Finally, a comparison of results for processing time between a CPU-based UPI system and the novel FPGA-based system were presented to justify the objective of this research.

• Journal of the Korea Society of Computer and Information
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• v.7 no.4
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• pp.115-120
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• 2002

This paper presents the implementation of IS-95 CDMA signal processor, baseband and Intermediate Frequency(IF) digital converter using Field Programmable Gate Array(FPGA) and ADC/DAC and frequency up/down converter IS-95 CDMA channel processor is generated the pilot channel signal with short PN code and Walsh-code generator. The digital If is composed of FPGA. digital transmit/receive signal processor and high speed analog-to-digital converter(ADC) and digital-to-analog converter(DAC). The frequency up/down converter consisted of filter, mixer, digital attenuator and PLL is analog conversion between intermediate frequency(IF) and baseband. This implemented system can be deployed in the IS-95 CDMA base station device etc.