• Title/Summary/Keyword: FPGA acceleration

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Design of a Compact GPS/MEMS IMU Integrated Navigation Receiver Module for High Dynamic Environment (고기동 환경에 적용 가능한 소형 GPS/MEMS IMU 통합항법 수신모듈 설계)

  • Jeong, Koo-yong;Park, Dae-young;Kim, Seong-min;Lee, Jong-hyuk
    • Journal of Advanced Navigation Technology
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    • v.25 no.1
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    • pp.68-77
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    • 2021
  • In this paper, a GPS/MEMS IMU integrated navigation receiver module capable of operating in a high dynamic environment is designed and fabricated, and the results is confirmed. The designed module is composed of RF receiver unit, inertial measurement unit, signal processing unit, correlator, and navigation S/W. The RF receiver performs the functions of low noise amplification, frequency conversion, filtering, and automatic gain control. The inertial measurement unit collects measurement data from a MEMS class IMU applied with a 3-axis gyroscope, accelerometer, and geomagnetic sensor. In addition, it provides an interface to transmit to the navigation S/W. The signal processing unit and the correlator is implemented with FPGA logic to perform filtering and corrrelation value calculation. Navigation S/W is implemented using the internal CPU of the FPGA. The size of the manufactured module is 95.0×85.0×.12.5mm, the weight is 110g, and the navigation accuracy performance within the specification is confirmed in an environment of 1200m/s and acceleration of 10g.

A study of Acceleration Technology using a ASIC co-processor (ASIC 프로세서를 이용한 가속 기술에 관한 연구)

  • Cho, Hyeyoung;Kim, Sungho;Lee, Sik
    • Proceedings of the Korea Information Processing Society Conference
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    • 2009.11a
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    • pp.183-184
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    • 2009
  • 과학용 어플리케이션을 주로 사용하는 고성능 컴퓨팅 시장에서 연산 요구량이 증가하면서 연산 가속 기술에 대한 관심이 높아지고 있다. 컴퓨터 연산 가속의 대안으로 재설정가능반도체(FPGA)나 주문형 반도체(ASIC) 등의 전용 칩을 사용하거나 Cell 프로세서와 같이 비디오 게임용으로 개발된 게임 프로세서(Game Processor)를 과학 어플리케이션에 이용하려는 노력이 대두되고 있다. 이에 본 논문에서는 ASIC 프로세서를 이용한 대표적인 가속 프로세서인 Clearspeed Advanced e620을 대상으로 성능을 분석하고 그 타당성을 검토하였다.

A DSP-based Controller for a Small Humanoid Robot (DSP를 사용한 소형 인간형 로봇의 제어기)

  • Cho Jeong-San;Sung Young-Whee
    • Journal of the Institute of Convergence Signal Processing
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    • v.6 no.4
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    • pp.191-197
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    • 2005
  • Biped walking is the main feature of a humanoid robot. In a biped walking robot, there are many actuators to be controlled and many sensors to be interfaced. In this paper, we propose a DSP-based controller for a miniature biped walking robot with 21 RC servo motors. The proposed controller has a hierarchical structure; a host PC, a DSP-based main controller, and an auxiliary controller with an FPGA chip. The host PC generates and transmits the robot walking data for given walking parameters such as stride, walking period, etc. The main controller implemented with a TMS320LF2407A controls 21 RC servo motors via the auxiliary controller. We also perform some experiments for balancing motion and walking on a slope terrain with interfacing a 2-axis acceleration sensor and a TMS320LF2407A.

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Implementation of a 3D Graphics Hardwired T&L Accelerator based on a SoC Platform for a Mobile System (SoC 플랫폼 기반 모바일용 3차원 그래픽 Hardwired T&L Accelerator 구현)

  • Lee, Kwang-Yeob;Koo, Yong-Seo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.9
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    • pp.59-70
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    • 2007
  • In this paper, we proposed an effective T&L(Transform & Lighting) Processor architecture for a real time 3D graphics acceleration SoC(System on a Chip) in a mobile system. We designed Floating point arithmetic IPs for a T&L processor. And we verified IPs using a SoC Platform. Designed T&L Processor consists of 24 bit floating point data format and 16 bit fixed point data format, and supports the pipeline keeping the balance between Transform process and Lighting process using a parallel computation of 3D graphics. The delay of pipeline processing only Transform operation is almost same as the delay processing both Transform operation and Lighting operation. Designed T&L Processor is implemented and verified using a SoC Platform. The T&L Processor operates at 80MHz frequency in Xilinx-Virtex4 FPGA. The processing speed is measured at the rate of 20M Vertexes/sec.

Design and Implementation of CW Radar-based Human Activity Recognition System (CW 레이다 기반 사람 행동 인식 시스템 설계 및 구현)

  • Nam, Jeonghee;Kang, Chaeyoung;Kook, Jeongyeon;Jung, Yunho
    • Journal of Advanced Navigation Technology
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    • v.25 no.5
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    • pp.426-432
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    • 2021
  • Continuous wave (CW) Doppler radar has the advantage of being able to solve the privacy problem unlike camera and obtains signals in a non-contact manner. Therefore, this paper proposes a human activity recognition (HAR) system using CW Doppler radar, and presents the hardware design and implementation results for acceleration. CW Doppler radar measures signals for continuous operation of human. In order to obtain a single motion spectrogram from continuous signals, an algorithm for counting the number of movements is proposed. In addition, in order to minimize the computational complexity and memory usage, binarized neural network (BNN) was used to classify human motions, and the accuracy of 94% was shown. To accelerate the complex operations of BNN, the FPGA-based BNN accelerator was designed and implemented. The proposed HAR system was implemented using 7,673 logics, 12,105 registers, 10,211 combinational ALUTs, and 18.7 Kb of block memory. As a result of performance evaluation, the operation speed was improved by 99.97% compared to the software implementation.

Implementation of Fuzzy Self-Tuning PID and Feed-Forward Design for High-Performance Motion Control System

  • Thinh, Ngo Ha Quang;Kim, Won-Ho
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • v.14 no.2
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    • pp.136-144
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    • 2014
  • The existing conventional motion controller does not perform well in the presence of nonlinear properties, uncertain factors, and servo lag phenomena of industrial actuators. Hence, a feasible and effective fuzzy self-tuning proportional integral derivative (PID) and feed-forward control scheme is introduced to overcome these problems. In this design, a fuzzy tuner is used to tune the PID parameters resulting in the rejection of the disturbance, which achieves better performance. Then, both velocity and acceleration feed-forward units are added to considerably reduce the tracking error due to servo lag. To verify the capability and effectiveness of the proposed control scheme, the hardware configuration includes digital signal processing (DSP) which plays the main role, dual-port RAM (DPRAM) to guarantee rapid and reliable communication with the host, field-programmable gate array (FPGA) to handle the task of the address decoder and receive the feed-back encoder signal, and several peripheral logic circuits. The results from the experiments show that the proposed motion controller has a smooth profile, with high tracking precision and real-time performance, which are applicable in various manufacturing fields.

A Miniature Humanoid Robot That Can Play Soccor

  • Lim, Seon-Ho;Cho, Jeong-San;Sung, Young-Whee;Yi, Soo-Yeong
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.628-632
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    • 2003
  • An intelligent miniature humanoid robot system is designed and implemented as a platform for researching walking algorithm. The robot system consists of a mechanical robot body, a control system, a sensor system, and a human interface system. The robot has 6 dofs per leg, 3 dofs per arm, and 2 dofs for a neck, so it has total of 20 dofs to have dexterous motion capability. For the control system, a supervisory controller runs on a remote host computer to plan high level robot actions based on the vision sensor data, a main controller implemented with a DSP chip generates walking trajectories for the robot to perform the commanded action, and an auxiliary controller implemented with an FPGA chip controls 20 actuators. The robot has three types of sensors. A two-axis acceleration sensor and eight force sensing resistors for acquiring information on walking status of the robot, and a color CCD camera for acquiring information on the surroundings. As an example of an intelligent robot action, some experiments on playing soccer are performed.

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Semiconductor Characteristics and Design Methodology in Digital Front-End Design (Digital Front-End Design에서의 반도체 특성 연구 및 방법론의 고찰)

  • Jeong, Taik-Kyeong;Lee, Jang-Ho
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.10
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    • pp.1804-1809
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    • 2006
  • The aim of this Paper is to describe the implementation of a low-power digital front-End Design (FED) that will act as the core of a stand-alone Power dissipation methodology. The design of digital integrated circuits is a large and diverse area, and we have chosen to focus on low power FED. Designs are made from synthesized logic, and we need to consider the low power digital FED including input clock, buffer, latches, voltage regulator, and capacitance-to-voltage counter which have been integrated onto hish bandwidth communication chips and system. These single- chip micro instruments, implemented in a 0.12um CMOS technology operate with a single 0.9V supply voltage, and can be used to monitor dynamic and static power dissipation, Vesture, acceleration junction temperature (Tj), etc.