• Journal of the Institute of Convergence Signal Processing
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• v.12 no.2
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• pp.139-144
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• 2011

The modern digital logic technology does not yet satisfy the speed requirements of real-time DSP circuits due to synchronized operation of multiplication and accumulation. This operation degrades DSP performance. Therefore, the double-base number system (DBNS) has emerged in DSP system as an alternative methodology because of fast multiplication and hardware simplicity. In this paper, authors propose a novel multiplication architecture. One operand is an output of a flash analog-to-digital converter (ADC) in DBNS format, while the other operand is a coefficient in the IEEE standard floating-point number format. The DBNS digital output from ADC is produced through a new double base number encoder (DBNE). The multiplied output is in the format of the IEEE standard floating-point number (FPNS). The proposed circuits process multiplication and conversion together. Compared to a typical multiplier that uses the FPNS, the proposed multiplier also consumes 45% less gates, and 44% faster than the FPNS multiplier on Spartan-3 FPGA board. The design is verified with FIR filter applications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.2
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• pp.366-373
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• 2007

In this paper we propose a multi-channel speech pickup system for calling quality enhancement of hands-free communication using ALTERA Nios-II processor. Multi-channel speech pickup system uses Delay-and-Sum beamformer with zero-padding interpolator. This paper implements speech pickup system using the Nios-II processor with real-time I/O data processing speed. The proposes speech pickup embedded system shows a good agreement with those of computer simulation(MATLAB) and conventional DSP processor(TMS320C6711) result. The proposed method is effective more than previous methods in cost and design processing time. As a result, LE(Logic Element) of hardware used 3,649/5,980(61%) on a chip.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1458-1466
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• 2019

Multilevel inverters have appeared as a successful and utilitarian solution in many power applications. The prime objective of an inverter is to keep the fundamental component of the output voltage of a multilevel inverter at a preferred value. Equally important is the need to keep the harmonic components in the output voltage within stated harmonic limits. Therefore, the basis of this research is to develop a harmonic minimization function that optimizes the switching angles of cascaded H-bridge multilevel inverter. Due to benefits of the Cuckoo Search (CS) algorithm, it is applied to determine the switching angles, which are further used to generate the switching pattern for firing the H-bridges of multilevel inverter. Simulation results are compared with SPWM based firing scheme. The switching frequency for SPWM firing scheme is taken as 200 Hz since the switching losses are increased when switching frequency is high. To validate the ability of Cuckoo Search optimized firing scheme in minimization of harmonics, experimental results obtained from hardware prototype of Five Level Cascaded H-Bridge Multilevel Inverter equipped with a FPGA controller are presented to verify the simulation results.

• Journal of the Korea Society of Computer and Information
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• v.23 no.1
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• pp.25-32
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• 2018

In this paper, we propose an edge detection algorithm for auto focus of infrared camera. We designed and implemented the edge detection of infrared image by using a spatial filter on FPGA. The infrared camera should be designed to minimize the image processing time and usage of hardware resource because these days surveillance systems should have the fast response and be low size, weight and power. we applied the $3{\times}3$ mask filter which has an advantage of minimizing the usage of memory and the propagation delay to process filtering. When we applied Laplacian filter to extract contour data from an image, not only edge components but also noise components of the image were extracted by the filter. These noise components make it difficult to determine the focus state. Also a bad pixel of infrared detector causes a problem in detecting the edge components. So we propose an adaptive edge detection filter that is a method to extract only edge components except noise components of an image by analyzing a variance of pixel data in $3{\times}3$ memory area. And we can detect the bad pixel and replace it with neighboring normal pixel value when we store a pixel in $3{\times}3$ memory area for filtering calculation. The experimental result proves that the proposed method is effective to implement the edge detection for auto focus in infrared camera.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.3
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• pp.157-163
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• 2019

A small millimeter-wave tracking radar is a pulse radar that searches, detects, and tracks a target in real time through a TWS (Track While Scan) method on a sea-going traps target with a large RCS running at low speed. This paper describes the development of a simulated signal generator to verify the performance of a small millimeter wave tracking radar in laboratory anechoic chamber environment. We describe a GUI program for testing and performance analysis in conjunction with hardware configuration and tracking radar, and verified the simulated signal generator implemented through performance test.

• Journal of IKEEE
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• v.23 no.3
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• pp.1068-1076
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• 2019

Most of the electronics we use today have built-in microcontrollers, which are called embedded systems. In such a small environment, responsiveness is very important for the microcontroller. In this paper, the basic input/output control, timer/counter interrupt operation principle, and understanding of the microcontroller are described. Program logic is proposed to improve throughput and latency by controlling characteristics of service routine and program execution order. The hardware simulations in this paper were verified using ATmega128 and PIC16F877A from Atmel and Microchip.

• Journal of Power Electronics
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• v.19 no.2
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• pp.475-486
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• 2019

This paper proposes the modulation and control of a three-to-six-phase matrix converter with an asymmetrical six-phase output. The matrix converter (MC) outputs consist of two sets of three-phase spatially shifted by $30^0$, where the two sets have two isolated neutrals. The space vector approach is considered for the modeling and subsequent modulation of the three-to-six phase MC. The intelligent selection of voltage space vectors is made to synthesize the reference voltages and to obtain a sinusoidal output. The dwell times of selected voltage space vectors are adjusted in such a way that the effect of the second and the third auxiliary plane vectors (i.e., x1-y1, and x2-y2) are nullified. To achieve the maximum output voltage gain and to ensure that no reactive power is drawn from the utility supply, the input side power factor is maintained at unity. Nevertheless, the source side power factor is controllable. The modulation technique is implemented in dSPACE working in conjunction with a FPGA. Hardware results that validate the proposed control algorithm are discussed.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.12
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• pp.5654-5668
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• 2018

Driven by security and real-time demands of Internet of Things (IoT), the timing of fog computing and edge computing have gradually come into place. Gateways bear more nearby computing, storage, analysis and as an intelligent broker of the whole computing lifecycle in between local devices and the remote cloud. In fog computing, the edge broker requires X-aware capabilities that combines software programmability, stream processing, hardware optimization and various connectivity to deal with such as security, data abstraction, network latency, service classification and workload allocation strategy. The prosperous of Field Programmable Gate Array (FPGA) pushes the possibility of gateway capabilities further landed. In this paper, we propose a software-defined gateway (SDG) scheme for fog computing paradigm termed as Fog Computing Zero-Knowledge Gateway that strengthens data protection and resilience merits designed for industrial internet of things or highly privacy concerned hybrid cloud scenarios. It is a proxy for fog nodes and able to integrate with existing commodity gateways. The contribution is that it converts Privacy-Enhancing Technologies rules into provable statements without knowing original sensitive data and guarantees privacy rules applied to the sensitive data before being propagated while preventing potential leakage threats. Some logical functions can be offloaded to any programmable micro-controller embedded to achieve higher computing efficiency.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.11a
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• pp.1525-1527
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• 2013

본 논문에서는 저시력자의 개선된 독서 환경을 제공하는 시각보조기기를 위한 실시간 영상처리 SoC(System on Chip) 하드웨어 구조 설계에 대해서 기술한다. 기존의 시각보조기기는 화면 영상이 실제 움직임보다 늦게 출력되는 잔상 현상이 발생하며, 색 변환 기능도 제한적이다. 따라서 본 논문에서 제안하는 실시간 영상처리 SoC 하드웨어 구조는 데이터 연산을 최소화함으로써 잔상 현상이 감소되며, 저시력자를 위한 다양한 색상 모드를 지원한다. 제안하는 영상처리 SoC 하드웨어 구조는 Core-A 모듈, Memory Controller 모듈, AMBA AHB bus 모듈, ISP(Image Signal Processing) 모듈, TFT-LCD Controller 모듈, VGA Controller 모듈, CIS Controller 모듈, UART 모듈, Block Memory 모듈로 구성된다. 시각보조기기를 위한 실시간 영상처리 SoC 하드웨어 구조는 Virtex4 XC4VLX80 FPGA 디바이스를 이용하여 검증하였으며, TSMC 180nm 셀 라이브러리로 합성한 결과 동작주파수는 54MHz, 게이트 수 197k이다.

• Journal of IKEEE
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• v.26 no.3
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• pp.437-444
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• 2022

This paper proposes a CRC error verification method for SPI and I2C buses of automotive semiconductors. In automotive semiconductors, when an error occurs in communication and an incorrect value is transmitted, fatal results may occur. Unlike LIN communication and CAN communication, in communication such as SPI and I2C, there is no frame for detecting an error, so some definitions of new standards are required. Therefore, in this paper, the CRC error detection mode is newly defined in the SPI and I2C communication protocols, and the verification is presented by designing it in hardware.