• Journal of Institute of Control, Robotics and Systems
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• v.8 no.1
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• pp.54-59
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• 2002

In the three-axis control of satellites by using on-board actuators, gyros are usually used to measure the attitude angles and angular rates. The gyros are operated by electronic parts and mechanical actuators. The digital components of the electronic parts consist of largely FPGA (Field Programmable Gate Array) as one of the methods for VLSI(Very Large Scale Integrated) circuit design, while the mechanical parts provide output signal directly by mechanical actuation of a spinning rotor. In this research, a mixed mode of gyro is implemented in FGA. In addition to the hardware implementation, the simulation study was conducted by using the SABER for the mixed mode simulator. Results for the practical implementation of the satellite ACS (Attitude Control System) interfaced with the data processing are also presented to validate the FPGA implementation.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2315-2318
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• 2003

The Wavelet Transform has been applied in mathematics and computer sciences. Numerous studies have proven its advantages in image processing and data compression, and have made it a basic encoding technique in data compression standards like JPEG2000 and MPEG-4. Software implementations of the Discrete Wavelet Transform (DWT) appears to be the performance bottleneck in real-time systems in terms of performance. And hardware implementations are not flexible. Therefore, FPGA implementations of the DWT has been a topic of recent research. The goal of this thesis is to investigate of FPGA implementations of the DWT Processor for image compression applications. The DWT processor design is based on the Lifting Based Wavelet Transform Scheme, which is a fast implementation of the DWT The design uses various techniques. The DWT Processor was simulated and implemented in a FLEX FPGA platform of Altera

• Proceedings of the Korea Information Processing Society Conference
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• 2003.05a
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• pp.397-400
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• 2003

FPGA 보드를 이용하여 디지털 논리 설계를 검증하려면 고가의 논리 분석기 장비를 필요로 한다. 본 논문은 FPGA 설계에 대한 검증을 PC에서 직접 입력 데이터를 FPGA 보드 쪽으로 전달하고 그 결과를 다시 PC 쪽에서 GUI 형태로 확인할 수 있도록 구성된, 논리 분석기 기능을 갖는 VHDL 모듈과 소프트웨어의 구현에 관한 것이다. 이와 같은 VHDL 모듈과 소프트웨어 모듈을 활용함으로써 추가 비용 없이 검증 과정을 수행할 수 있다.

• Journal of Information Processing Systems
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• v.15 no.4
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• pp.890-903
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• 2019

The single carrier frequency domain equalization (SC-FDE) technology is an important part of the broadband wireless access communication system, which can effectively combat the frequency selective fading in the wireless channel. In SC-FDE communication system, the accuracy of timing synchronization directly affects the performance of the SC-FDE system. In this paper, on the basis of Schmidl timing synchronization algorithm a timing synchronization algorithm suitable for FPGA (field programmable gate array) implementation is proposed. In the FPGA implementation of the timing synchronization algorithm, the sliding window accumulation, quantization processing and amplitude reduction techniques are adopted to reduce the complexity in the implementation of FPGA. The simulation results show that the algorithm can effectively realize the timing synchronization function under the condition of reducing computational complexity and hardware overhead.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.2
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• pp.435-442
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• 2018

This study implemented an FPGA-based system to extract PCB defect patterns. The FPGA-based system can perform pattern matching at high speed for vision automation. An image processing library that is used to extract defect patterns was also implemented in IPs to optimize the system. The IPs implemented are Camera Link IP, Histogram IP, VGA IP, Horizontal Projection IP and Vertical Projection IP. In terms of hardware, the FPGA chip from the Vertex-5 of Xilinx was used to receive and handle images that are sent from a digital camera. This system uses MicroBlaze CPU. The image results are sent to PC and displayed on a 7inch TFT-LCD and monitor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.4
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• pp.888-894
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• 2015

This paper describes an efficient hardware design of Lightweight Encryption Algorithm (LEA) developed by National Security Research Institute(NSRI). The LEA crypto-processor supports for master key of 128-bit. To achieve small-area and low-power implementation, an efficient hardware sharing is employed, which shares hardware resources for encryption and decryption in round transformation block and key scheduler. The designed LEA crypto-processor was verified by FPGA implementation. The LEA core synthesized with Xilinx ISE has 1,498 slice elements, and the estimated throughput is 216.24 Mbps with 135.15 MHz.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.4
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• pp.1-8
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• 2001

In this paper we propose high performance system with reduced hardware architecture to convert a color tone. Conversion for the color tone of a input image is necessary to calculate the color temperature of the image Conventional way of calculating the temperature uses algorithm using the method calculating 2-D chromaticity coordinates. But it requires bulky hardware[1]. This paper propose the color temperature calculation method about 1-D chromaticity coordinates that reduces the hardware complexity while keeping the performance of the 2-D color temperature algorithm . The proposed method is verified by fLCD-TV system using the Xilinx Virtex FPGA XCV 2000E-6BG560 that has 1344*806 resolution and requires a high-speed 65MHz operation.

• Journal of IKEEE
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• v.24 no.1
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• pp.243-247
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• 2020

As the autonomous driving market is rapidly growing, research on autonomous driving is being conducted. Self-driving functions should be performed regardless of the weather for the driver's safety. However, misty weather is difficult to autonomous driving because of the lack of visibility, so a defog algorithm should be used. The image obtained through the fog removal algorithm causes the image quality to deteriorate. To improve this problem, HSV color correction is used to increase the sharpness. In this paper, we propose a color correction hardware using HSV that can cope with 4K images. The hardware was designed with Verilog and verified by Modelsim. In addition, the FPGA was implemented with the goal of Xilinx's xc7z045-2ffg900.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.777-779
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• 2014

The LEA(Lightweight Encryption Algorithm) is a 128-bit high-speed/lightweight block cipher algorithm developed by National Security Research Institute(NSRI) in 2012. The LEA encrypts plain text of 128-bit using cipher key of 128/192/256-bit, and produces cipher text of 128-bit, and vice versa. To reduce hardware complexity, we propose an efficient architecture which shares hardware resources for encryption and decryption in round transformation block. Hardware sharing technique for key scheduler was also devised to achieve area-efficient and low-power implementation. The designed LEA cryptographic processor was verified by using FPGA implementation.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.6
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• pp.79-89
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• 2004

Fingerprint identification consists of user enrollment phase storing user's fingerprint in a database and user identification phase making a candidate list for a given fingerprint. straightforward approach to perform the user identification phase is to scan the entire database sequentially, and takes times for large-scale databases. In this paper, we develop a hardware design which can perform the user identification phase in real-time. Our design employs parallel processing techniques and has been implemented on a PCI-based platform containing an FPGA and SDRAMs. Based on the performance evaluation, our hardware implementation can provide a scalability and perform the fingerprint identification in real-time.