• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1527-1539
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• 2015

In this paper the hardware implementation of the direct torque control based on the fuzzy logic technique of induction motor on the Field-Programmable Gate Array (FPGA) is presented. Due to its complexity, the fuzzy logic technique implemented on a digital system like the DSP (Digital Signal Processor) and microcontroller is characterized by a calculating delay. This delay is due to the processing speed which depends on the system complexity. The limitation of these solutions is inevitable. To solve this problem, an alternative digital solution is used, based on the FPGA, which is characterized by a fast processing speed, to take the advantage of the performances of the fuzzy logic technique in spite of its complex computation. The Conventional Direct Torque Control (CDTC) of the induction machine faces problems, like the high stator flux, electromagnetic torque ripples, and stator current distortions. To overcome the CDTC problems many methods are used such as the space vector modulation which is sensitive to the parameters variations of the machine, the increase in the switches inverter number which increases the cost of the inverter, and the artificial intelligence. In this paper an intelligent technique based on the fuzzy logic is used because it is allows controlling the systems without knowing the mathematical model. Also, we use a new method based on the Xilinx system generator for the hardware implementation of Direct Torque Fuzzy Control (DTFC) on the FPGA. The simulation results of the DTFC are compared to those of the CDTC. The comparison results illustrate the reduction in the torque and stator flux ripples of the DTFC and show the Xilinx Virtex V FPGA performances in terms of execution time.

• Journal of Computing Science and Engineering
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• v.12 no.1
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• pp.24-35
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• 2018

Deep convolutional neural network (DCNN) is an advanced technology in image recognition. Because of extreme computing resource requirements, DCNN implementation with software alone cannot achieve real-time requirement. Therefore, the need to implement DCNN accelerator hardware is increasing. In this paper, we present a field programmable gate array (FPGA)-based hardware accelerator design of DCNN targeting handwritten Hangul character recognition application. Also, we present design optimization techniques in SDAccel environments for searching the optimal FPGA design space. The techniques we used include memory access optimization and computing unit parallelism, and data conversion. We achieved about 11.19 ms recognition time per character with Xilinx FPGA accelerator. Our design optimization was performed with Xilinx HLS and SDAccel environment targeting Kintex XCKU115 FPGA from Xilinx. Our design outperforms CPU in terms of energy efficiency (the number of samples per unit energy) by 5.88 times, and GPGPU in terms of energy efficiency by 5 times. We expect the research results will be an alternative to GPGPU solution for real-time applications, especially in data centers or server farms where energy consumption is a critical problem.

• Journal of IKEEE
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• v.24 no.1
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• pp.52-58
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• 2020

This paper describes a hardware implementation of a true random number generator (TRNG) for information security applications. A new approach for TRNG design was proposed by adopting random transition rules in cellular automata and applying different transition rules at every time step. The TRNG circuit was implemented on Spartan-6 FPGA device, and its hardware operation generating random data with 100 MHz clock frequency was verified. For the random data of 2×10⁷ bits extracted from the TRNG circuit implemented in FPGA device, the randomness characteristics of the generated random data was evaluated by the NIST SP 800-22 test suite, and all of the fifteen test items were found to meet the criteria. The TRNG in this paper was implemented with 139 slices of Spartan-6 FPGA device, and it offers 600 Mbps of the true random number generation with 100 MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.69-78
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• 2001

This paper presents the design and FPGA implementation of a FLEX PSP(Protocol Signal Processor) for the portable high speed paging system. In this approach, two algorithms are newly proposed for implementing the PSP which provides capabilities of the maximum 6,400bps at speed, high-channel throughput, real time error correction and an effective frame search function. One is an accurate symbol synchronization algorithm which is applied for synchronizing the interleaved 4-level bit symbols which are received at input stage of A/D converter, and the other is a modified fast decoding algorithm which is provided for realizing double error correction of (31,21)BCH signal. The PSP is composed of six functional modules, and each module is modelled in VHDL(VHSIC Hardware Description Language). Both functional simulation and logic synthesis have performed for the proposed PSP through the use of Synopsys$^{TM}$ tools on a Axil-320 Workstation, and where Altera 10K libraries are used for logic synthesis. From logic synthesis, we can see that the number of gates is about 2,631. For FPGA implementation, timing simulation is performed by using Altera MAX+ PLUS II, and its results will be also given. The PSP which is implemented in 6 FPGA devices on a PCB has been verified by means of Logic Analyzer.r.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.12
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• pp.1882-1889
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• 2021

This paper describes a high-performance hardware implementation of modular multiplication used as a core operation in elliptic curve cryptography. A 521-bit high-performance modular multiplier for NIST P-521 curve was designed by adopting 3-way Toom-Cook integer multiplication and fast reduction algorithm. Considering the property of the 3-way Toom-Cook algorithm in which the result of integer multiplication is multiplied by 1/3, modular multiplication was implemented on the Toom-Cook domain where the operands were multiplied by 3. The modular multiplier was implemented in the xczu7ev FPGA device to verify its hardware operation, and hardware resources of 69,958 LUTs, 4,991 flip-flops, and 101 DSP blocks were used. The maximum operating frequency on the Zynq7 FPGA device was 50 MHz, and it was estimated that about 4.16 million modular multiplications per second could be achieved.

• The Journal of the Convergence on Culture Technology
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• v.9 no.5
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• pp.517-522
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• 2023

Existing radars have been developed by applying RF sub-array algorithms, and recently, fully digital Multiple-Input Multiple-Output (MIMO) radar algorithms have been implemented for vehicle radars. In this paper, the radar algorithm applying the Phased MIMO method to the hardware of the RF sub-array method, which is an unsecured technology, was implemented and verified in real time. In order to secure RF sub-array Phased MIMO algorithm technology, a hardware structure for FPGA-based real-time signal processing was presented, and performance was first predicted through design and simulation. Through this, the digital signal of FPGA-based broadband MIMO FMCW radar The processing hardware was developed, and the Phased MIMO radar algorithm of the RF sub-Array method was finally implemented and verified in real time. Based on this, it is judged that it will be possible to secure and apply core technologies necessary for terahertz band radar in the future.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.7
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• pp.402-413
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• 2004

This paper presents an Implementation of Korean standard 128-bit block cipher SEED for the small (8 or 16-bits) embedded system using a low-cost FPGA(Field Programmable Gate Array) chip. Due to their limited computing and storage capacities most of the 8-bits/16-bits small embedded systems require a separate and dedicated cryptography processor for data encryption and decryption process which require relatively heavy computation job. So, in order to integrate the SEED with other logic circuit block in a single chip we need to invent a design which minimizes the area demand while maintaining the proper performance. But, the straight-forward mapping of the SEED specification into hardware design results in exceedingly large circuit area for a low-cost FPGA capacity. Therefore, in this paper we present a design which maximize the resource sharing and utilizing the modern FPGA features to reduce the area demand resulting in the successful implementation of the SEED plus interface logic with single low-cost FPGA. We achieved 66% area accupation by our SEED design for the XC2S100 (a Spartan-II series FPGA from Xilinx) and data throughput more than 66Mbps. This Performance is sufficient for the small scale embedded system while achieving tight area requirement.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.187-192
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• 2014

Various researches are performed to extract significant features from continuous images. The FAST algorithm has the simple structure for arithmetic operation and it is easy to extraction the features in real time. For this reason, the FPGA based hardware accelerator is implemented and widely applied for the FAST algorithm. The hardware accelerator needs the threshold to extract the features from images. The threshold is influenced not only the number of extracted features but also the total execution time. Therefore, the way of threshold control is important to stabilize the total execution time and to extract features as much as possible. In order to control the threshold, this paper proposes the PI controller. The function and performance for the proposed PI controller are verified by using test images and the PI control logic is designed based on Xilinx Vertex IV FPGA. The proposed scheme can be implemented by adding 47 Flip Flops, 146 LUTs, and 91 Slices to the FAST hardware accelerator. This proposed approach only occupies 2.1% of Flip Flop, 4.4% of LUTs, and 4.5% of Slices and can be regarded as a small portion of hardware cost.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1254-1258
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• 2004

This paper presents of position control of Permanent Magnet Synchronous Motor (PMSM) the implementation with Field Programmable Gate Array (FPGA) is proposed. Cascade control with inner loop as a current control and an outer loop as a position control is chosen for simplicity and fast response. FPGA is a single chip (single processing unit), which will perform the following tasks: receive and convert control signal, create a reference current signal, control current and create switch signal and act as position controller in a addition of zero form. The 10 kHz sampling frequency and 25 bit of floating point data are defined in this implementation.The experimental results show that the performance of FPGA based position control is comparable with the hardware based position control, with the advantage of control algorithm flexibility

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.165-171
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• 1996

A noncoherent full-digital PN(pseudo noise) code acquisition/tracking loop has been presetned and implemented in FPGA for the CDMA band-limited direct-sequence spread-spectrum (DS-SS) signals. It employs a simple decimator to control of local PN code phase to lower the hardware cost, and a second order loop to enable the more accurate tracking. The proposed acquisition/tracking loop has been designed in RTL-level VHDL, synthesized into logic gates using the design analyzer of synopsys software, implemented in an ALTERA FPGA chip, and tested. The number of logic gates used in the implemented FPGA chip is around 7000. The functionality has been verified using a PC interface circuitry and a logic analyzer.