• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.263-266
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• 2012

This paper describes an efficient hardware implementation of Whirlpool hash function as ISO/IEC 10118-3 standard. Optimized timing is achieved by using pipelined small LUTs, and Whirlpool block cipher and key schedule have been implemented in parallel for improving throughput. In key schedule, key addition is area-optimized by using inverters and muxes instead of using rom and xor gates. This hardware has been implemented on Virtex5-XC5VSX50T FPGA device. Its maximum operating frequency is about 151MHz, and throughput is about 950Mbps.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6C
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• pp.498-504
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• 2008

In this paper, an efficient hardware platform for the digital signal processing for OFDM Communication systems is presented. The hardware platform consists of a single FPGA, two DSPs with 8000 MIPS of maximum at 1 GHz clock, 2-channel ADC and DAC supporting maximum 125 MHz sampling rate, and flexible data bus architecture, so that a wide variety of baseband signal processing algorithms for practical OFDM communication systems may be implemented and tested. The IEEE 802.16 software modem is also presented in order to verify the effectiveness and usefulness of the designed platform.

• ETRI Journal
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• v.33 no.5
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• pp.731-740
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• 2011

Reconfigurable computing using a field-programmable gate-array (FPGA) device has become a promising solution in system design because of its power efficiency and design flexibility. To bring the benefit of FPGA to many application programmers, there has been intensive research about automatic translation from high-level programming languages (HLL) such as C and C++ into hardware. However, the large gap of syntaxes and semantics between hardware and software programming makes the translation challenging. In this paper, we introduce a new approach for the translation by using the widely used GCC compiler. By simply adding a hardware description language (HDL) backend to the existing state-of- the-art compiler, we could minimize an effort to implement the translator while supporting full features of HLL in the HLL-to-HDL translation and providing high performance. Our translator, called GCC2Verilog, was implemented as the GCC's cross compiler targeting at FPGAs instead of microprocessor architectures. Our experiment shows that we could achieve a speedup of up to 34 times and 17 times on average with 4-port memory over PICO microprocessor execution in selected EEMBC benchmarks.

• The Journal of the Korea Contents Association
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• v.9 no.9
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• pp.51-59
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• 2009

A watermarking for copyright protection of digital contents for broadcasting have to be made for a real-time system. In this paper, we propose a real-time video watermarking system which is hardware-based watermarking system of SD/HD (standard definition/high definition) video with the STRATIX FPGA device from ALTERA. There was little visual artifact due to watermarking in subjective quality evaluation between the original video and the watermarked one in our experiment. Embedded watermark was extracted after robustness testscalled natural video attacks such as A/D (analog/digital) conversion. Our implemented watermarking hardware system can be useful in movie production and broadcasting companies that requires real-time contents protection systems.

• Journal of IKEEE
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• v.20 no.4
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• pp.398-411
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• 2016

SVM, a machine learning method, is widely used in image processing for it's excellent generalization performance. However, to add other data to the pre-trained data of the system, we need to train the entire system again. This procedure takes a lot of time, especially in embedded environment, and results in low performance of SVM. In this paper, we implemented an SVM trainer and classifier in an FPGA to solve this problem. We parlallelized the repeated operations inside SVM and modified the exponential operations of the kernel function to perform fixed point modelling. We implemented the proposed hardware on Xilinx ZC 706 evaluation board and used TSR algorithm to verify the FPGA result. It takes about 5 seconds for the proposed hardware to train 2,000 data samples and 16.54ms for classification for $1360{\times}800$ resolution in 100MHz frequency, respectively.

• Journal of IKEEE
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• v.20 no.4
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• pp.344-350
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• 2016

In this Paper, we propose an optimized method of hardware design based on Field Programmable Gate Array (FPGA) to detect rotated angle of high definition image about Extreme Contour Point (ECP) algorithm with moving video image could be not happened to translation motion, but also physical rotation motion. It was evaluated by XC7Z020 xc7z020-3clg400 FPGA board by using xilinx 14.2 tool. The much well-known method, the Coordinate Rotation Digital Integrated Computation (CORDIC) is an algorithm to estimate rotated angle between point and point. Through the result both ECP and CORDIC, our proposed design are confirmed to have similar operating speed of about 4ns with CORDIC. However, it is verified to have high performance result in terms of the hardware cost, is much better than CORDIC with cost reduction of registers and Look Up Tables (LUTs) of 108% and 91%, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.10C
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• pp.813-819
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• 2008

In this paper, we implemented a real-time system which displays 3-dimensional (3D) stereoscopic image with stereo camera. The system consists of a set of stereo camera, FPGA board, and 3D stereoscopic LCD. Two CMOS image sensor were used for the stereo camera. FPGA which processes video data was designed with Verilog-HDL, and it can accommodate various resolutional videos. The stereoscopic image is configured by two methods which are side-by-side and up-down image configuration. After the left and right images are converted to the type for the stereoscopic display, they are stored into SDRAM. When the next frame is inputted into FPGA from two CMOS image sensors, the previous video data is output to the DA converter for displaying it. From this pipeline operation, the real-time operation is possible. After the proposed system was implemented into hardware, we verified that it operated exactly.

• Journal of international Conference on Electrical Machines and Systems
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• v.3 no.2
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• pp.110-115
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• 2014

The reconfigurability of FPGA devices allows designers to evaluate, test and validate a new control algorithm; a new component or prototypes without damaged the real system with the so-called hardware co-simulation. The present paper uses the Xilinx System Generator (XSG) environment to establish and validate a new nonlinear estimator for the rotor time constant inverse that will be exploited to improve the indirect rotor field control of induction motor.

• ETRI Journal
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• v.39 no.4
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• pp.525-534
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• 2017

A hardware-acceleration architecture that separates virtual network functions (VNFs) and network control (called HSN) is proposed to solve the mismatch between the simple flow steering requirements and strong packet processing abilities of software-defined networking (SDN) forwarding elements (FEs) in SDN/network function virtualization (NFV) architecture, while improving the efficiency of NFV infrastructure and the performance of network-intensive functions. HSN makes full use of FEs and accelerates VNFs through two mechanisms: (1) separation of traffic steering and packet processing in the FEs; (2) separation of SDN and NFV control in the FEs. Our HSN prototype, built on NetFPGA-10G, demonstrates that the processing performance can be greatly improved with only a small modification of the traditional SDN/NFV architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.7B
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• pp.996-1005
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• 2001

본 논문에서는 ASIC 벤더의 셀 라이브러리와 MUX-based FPGA에 있는 고정된 입력을 갖는 연결구조의 수를 최소화하는 하드웨어 할당 알고리듬을 제안한다. 제안된 할당 알고리듬은 연산자간을 연결하는 신호선이 반복적으로 이용되어 연결 신호선 수가 최소가 될 수 있도록 연산자를 할당한다. 연결 구조를 고려한 이분할 그래프에 가중치를 설정하고 변수와 레지스터간의 최대 가중치 매칭을 구함으로써 레지스터 할당을 수행한다. 또한 연결구조에 대한 멀티플렉서의 중복 입력을 제거하고 연산자에 연결된 멀티플렉서간의 입력을 교환하는 입력 정렬 과정으로 연결구조를 최소화한다. 벤치마크 실험을 통하여 제안된 알고리즘의 효용성을 보인다.