• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.2
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• pp.268-275
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• 2020

A lightweight hardware design of self-timed ring based true random number generator (TRNG) suitable for information security applications is described. To reduce hardware complexity of TRNG, an entropy extractor with feedback structure was proposed, which minimizes the number of ring stages. The number of ring stages of the FSTR-TRNG was determined to be a multiple of eleven, taking into account operating clock frequency and entropy extraction circuit, and the ratio of tokens to bubbles was determined to operate in evenly-spaced mode. The hardware operation of FSTR-TRNG was verified by FPGA implementation. A set of statistical randomness tests defined by NIST 800-22 were performed by extracting 20 million bits of binary sequences generated by FSTR-TRNG, and all of the fifteen test items were found to meet the criteria. The FSTR-TRNG occupied 46 slices of Spartan-6 FPGA device, and it was implemented with about 2,500 gate equivalents (GEs) when synthesized in 180 nm CMOS standard cell library.

• Nuclear Engineering and Technology
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• v.54 no.7
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• pp.2444-2452
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• 2022

The field-programmable gate array (FPGA) is gaining popularity in industrial automation such as nuclear power plant instrumentation and control (I&C) systems due to the benefits of having non-existence of operating system, minimum software errors, and minimum common reason failures. Separate functions can be processed individually and in parallel on the same integrated circuit using FPGAs in comparison to the conventional microprocessor-based systems used in any plant operations. The use of FPGAs offers the potential to minimize complexity and the accompanying difficulty of securing regulatory approval, as well as provide superior protection against obsolescence. Wireless sensor networks (WSNs) are a new technology for acquiring and processing plant data wirelessly in which sensor nodes are configured for real-time signal processing, data acquisition, and monitoring. ZigBee (IEEE 802.15.4) is an open worldwide standard for minimum power, low-cost machine-to-machine (M2M), and internet of things (IoT) enabled wireless network communication. It is always a challenge to follow the specific topology when different Zigbee nodes are placed in a large network such as a plant. The research article focuses on the hardware chip design of different topological structures supported by ZigBee that can be used for monitoring and controlling the different operations of the plant and evaluates the performance in Vitex-5 FPGA hardware. The research work presents a strategy for configuring FPGA with ZigBee sensor nodes when communicating in a large area such as an industrial plant for real-time monitoring.

• Journal of information and communication convergence engineering
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• v.18 no.1
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• pp.1-7
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• 2020

This paper proposes a fast-processing and low-cost hardware multiple input multiple output (MIMO) channel emulator. The channel emulator is an important component of hardware-based simulation systems. The novelty of this work is the use of sharing and pipelining functions to reduce hardware resource utilization while maintaining a high sample rate. In our proposed emulator, the samples are created sequentially and interpolated to ensure the sample rate is equal to the base band rate. The proposed 4 × 4 MIMO requires low-cost hardware resource so that it can be implemented on a single field-programmable gate array (FPGA) chip. An implementation on Xilinx Virtex-7 VX980T was found to occupy 10.47% of the available configurable slice registers and 12.58% of the FPGA's slice lookup tables. The maximum frequency of the proposed emulator is 758.064 MHz, so up to 560 different paths can be processed simultaneously to generate 560 × 758 million × 2 × 32 bit complex-valued fading samples per second.

• Journal of IKEEE
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• v.23 no.3
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• pp.984-987
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• 2019

Recently, autonomous driving technology based on object recognition and lane recognition has attracted attention. However, in foggy weather, haze removal technology is needed because it is difficult to recognize surrounding objects. The technology of removing hazy is currently being studied in many ways, and a single image based haze removal algorithms are typical. In this paper, we design the hardware for haze removal by estimating the hazy partical map. Proposed hardware architecture is designed to have a cumulative histogram based filter that does not affect the hardware size even if the window size of filter increases. The hardware design is implemented with XILINX's xc7z045-ffg900 as the target board.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.152.4-152
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• 2001

We investigate, in this paper, the use of FPGA(Field Programmable Gate Array) architectures for real-time processing of digital linescan camera. The use of FPGAS for low-level processing represents an excellent tradeoff between software and special purpose hardware implementations. A library of modules that implement common low-level machine vision operations is presented. These modules are designed with gate-level hardware components that are compiled into the functionality of the FPGA chips. This new synchronous unidirectional interface establishes a protocol for the transfer of image and result data between modules. This reduces the design complexity and allows several different low-level operations to be applied to the same input image ...

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.281-284
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• 2002

Rijndael algorithm is known to a new private key block cipher which is substitute for DES. Rijndael algorithm is adequate to both hardware and software implementation, so hardware implementation of Rijndael algorithm is applied to high speed data encryption and decryption. This paper describes three implementation methods of Rijndael S-box, which is important factor in performance of Rijndael coprocessor. It shows synthesis results of each S-box implementation in Xilinx FPGA. Tllc lilree S-box implementation methods are implementation using lookup table only, implementation using both lookup table and combinational logic, and implementation using combinational logic only.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.7
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• pp.594-601
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• 2000

EIA-709.1 Control Network Protocol is the basic protocol of LonWorks systems that is emerg-ing as a fieldbus device. In this paper the protocol is implemented by using VHDL with FPGA and C program on an Intel 8051 processor. The protocol from the physical layer to the network layer of EIA-709.1 is im-plemented in a hardware level,. So it decreases the load of the CPU for implementing the protocol. We verify the commercial feasibility of the hardware through the communication test with Neuron Chip. based on EIA-709.1 protocol which is used in industrial fields. The developed protocol based on FPGA becomes one of IP can be applicable to various industrial field because it is implemented by VHDL.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7A
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• pp.683-694
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• 2002

In this paper, a digital image compression codec using 2D DWT(Discrete Wavelet Transform) is designed using the FPGA technology for real time operation The implemented image compression codec using wavelet decomposition consists of a wavelet kernel part for wavelet filtering process, a quantizer/huffman coder for quantization and huffman encoding of wavelet coefficients, a memory controller for interface with external memories, a input interface to process image pixels from A/D converter, a output interface for reconstructing huffman codes, which has irregular bit size, into 32-bit data having regular size data, a memory-kernel buffer to arrage data for real time process, a PCI interface part, and some modules for setting timing between each modules. Since the memory mapping method which converts read process of column-direction into read process of the row-direction is used, the read process in the vertical-direction wavelet decomposition is very efficiently processed. Global operation of wavelet codec is synchronized with the field signal of A/D converter. The global hardware process pipeline operation as the unit of field and each field and each field operation is classified as decomposition levels of wavelet transform. The implemented hardware used FPGA hardware resource of 11119(45%) LAB and 28352(9％) ESB in FPGA device of APEX20KC EP20k600CB652-7 and mapped into one FPGA without additional external logic. Also it can process 33 frames(66 fields) per second, so real-time image compression is possible.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.150-161
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• 2012

Eye detection is widely used in applications, such as face recognition, driver behavior analysis, and human-computer interaction. However, it is difficult to achieve real-time performance with software-based eye detection in an embedded environment. In this paper, we propose a parallel hardware architecture for real-time eye detection. We use the AdaBoost algorithm with modified census transform(MCT) to detect eyes on a face image. We parallelize part of the algorithm to speed up processing. Several downscaled pyramid images of the eye candidate region are generated in parallel using the input face image. We can detect the left and the right eye simultaneously using these downscaled images. The sequential data processing bottleneck caused by repetitive operation is removed by employing a pipelined parallel architecture. The proposed architecture is designed using Verilog HDL and implemented on a Virtex-5 FPGA for prototyping and evaluation. The proposed system can detect eyes within 0.15 ms in a VGA image.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.404-406
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• 2015

This paper describes a small-area hardware implementation of the block cipher algorithm CLEFIA-128 which supports for 128-bit master key. A compact structure using single data processing block is adopted, which shares hardware resources for round transformation and the generation of intermediate values for round key scheduling. In addition, data processing and key scheduling blocks are simplified by utilizing a modified GFN(generalized Feistel network) and key scheduling scheme. The CLEFIA-128 crypto-processor is verified by FPGA implementation. It consumes 823 slices of Virtex5 XC5VSX50T device and the estimated throughput is about 105 Mbps with 145 MHz clock frequency.