• Journal of IKEEE
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• v.15 no.1
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• pp.86-95
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• 2011

In this paper, we propose a testbed system for the crisis management system of the power grid(CMS-PG) using satellite communication network. For the verification of CMS-PG, the proposed system composed of the simulator of satellite communication network and the simulator of phase measurement unit. Proposed satellite communication simulator can evaluate the delay and the robustness of the communication according to the rainfall and the humidity of local site. And the proposed simulator can calculates the voltage stability by hardware implementation using FPGA. Using the proposed testbed system, we adapted its function of crisis management system for the conventional power grid.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.9
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• pp.1803-1810
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• 2009

This paper designed IQ imbalance estimator and compensator to cancel the IQ imbalance error in DVB-T system using OFDM by Matlab. Among Matlab model, we designed and implemented IQ imbalance estimator and compensator by System Generator of Xilinx and Matlab model compared with Xilinx System Generator Model for FPGA implementation. As a result of simulation, we confirmed that both model estimated and compensated IQ imbalance error very well. Also, we verified the performance through hardware co-simulation, timing analysis and resource estimation with Xilinx Spartan3 xc3s1000 fg676-4 target Device.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1332-1339
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• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• Annual Conference of KIPS
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• 2008.11a
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• pp.108-111
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• 2008

본 논문에서는 KLT(Kanade-Lucas-Tomasi) 추적기에서 특징점의 개수를 일정하게 유지시키기 위해 존재하는 특징점의 관리 부분을 FPGA(Field Programmable Gate Array)에 구현하기 위한 구조를 제안한다. FPGA 에 구현하기 위해 한정된 자원을 효과적으로 사용하도록 하는 것을 목표로 연산량이 많은 부분을 적은 연산량으로 구현 가능한 것으로 대체하고, 메모리의 크기와 접근 회수를 줄이기 위한 방법을 고려했다. 구현이 간단한 Harris 코너 검출기를 이용하여 특징점을 선택하고, 나눗셈 연산이 필요 없는 히스토그램을 이용하여 임계값을 설정해 특징점을 관리했다. C 언어로 시뮬레이션을 수행하여 제안한 방법을 확인했고, 기존의 특징점 관리 방법과의 비교를 통해 검증했다.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.81-88
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• 2004

In this paper, we designed the outer encoder/decoder for the terrestrial DMB that is an advanced digital broadcasting standard, implemented, and verified by using ALTERA FPGA. In the encoder part, it was created the parity bytes (16 bytes) from the input packet (188by1e) of MPEG-2 TS and the encoded data was distributed output by the convolutional interleaver for Preventing burst errors. In the decoder part, It was proposed the algorithm that detects synchronous character suitable to DMB in transmitted data from the encoder. The circuit complexity in RS decoder was reduced by applying a modified Euclid's algorithm. This system has a capability to correct error of the maximum 8 bytes in a packet. After the outer encoder/decoder algorithm was verified by using C language, described in VHDL and implemented in the ALTERA FPGA chips.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.7
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• pp.949-955
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• 2018

Hardware-in-the-loop (HIL) simulation is a technique that can be employed for developing and testing complex real-time embedded systems. HIL simulation provides an effective platform for verifying power management system (PMS) performance of liquefied natural gas carriers, which are high value-added vessels such as offshore plants. However, HIL tests conducted by research institutes, including domestic shipyards, can be protracted. To address the said issue, this study proposes a field programmable gate array (FPGA) based PMS-HIL simulator that comprises a power supply, consumer, control console, and main switchboard. The proposed HIL simulation platform incorporated actual equipment data while conducting load sharing PMS tests. The proposed system was verified through symmetric, asymmetric, and fixed load sharing tests. The proposed system can thus potentially replace the standard factory acceptance tests. Furthermore, the proposed simulator can be helpful in developing additional systems for vessel automation and autonomous operation, including the development of energy management systems.

• Review of KIISC
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• v.16 no.3
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• pp.25-33
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• 2006

본 논문에서는 임베디드 시스템 온칩 적용을 위한 통합 보안 프로세서를 SIP(Semiconductor Intellectual Property)로 설계하였다. 각각의 SIP는 VHDL RTL로 모델링하였으며, 논리합성, 시뮬레이션, FPGA 검증을 통해 재사용이 가능하도록 구현하였다. 또한 ARM9과 SIP들이 서로 통신이 가능하도록 AMBA AHB의 스펙에 따라 버스동작모델을 설계, 검증하였다. 플랫폼기반의 통합 보안 SIP는 ECC, AES, MD-5가 내부 코어를 이루고 있으며 각각의 SIP들은 ARM9과 100만 게이트 FPGA가 내장된 디바이스를 사용하여 검증하였으며 최종적으로 매그나칩 $0.25{\mu}m(4.7mm\times4.7mm)$ CMOS 공정을 사용하여 MPW(Multi-Project Wafer) 칩으로 제작하였다.

• Journal of Satellite, Information and Communications
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• v.10 no.3
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• pp.38-43
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• 2015

This paper describes a GPS signal generator that can generate multiple satellite signals in real time at the RF level. It realizes the verified software algorithm on a FPGA. The algorithm models orbits and environmental errors such as ionospheric and tropospheric multipath. The position of a simulated receiver is one of simulation parameters. The hardware which consists of a digital logic board and an analog board can generate 16 simulated satellites signals at the same time. The users can generate spoofing signals and jamming signals as well as satellite signals by using the windows-based control software. In addition, the software provides GIS-based simulation scenarios editing tools. We verified the generator by using commercial receivers. As an application, we configured generators as indoor positioning systems and tested them in a building. To improve the accuracy of indoor systems is our further study.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.2
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• pp.293-298
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• 2009

In this contribution, a 193-bit elliptic curve cryptography coprocessor was implemented on an FPGA board. Optimized algorithms and numerical expressions which had been verified through C program simulation, should be analyzed again with HDL (hardware description language) such as Verilog, so that the verified ones could be modified to be applied directly to hardware implementation. The reason is that the characteristics of C programming language design is intrinsically different from the hardware design structure. The hardware IP which was double-checked in view of hardware structure together with algoritunic verification, was implemented on the Altera CycloneII FPGA device equipped with ARM9 microprocessor core, to a real chip prototype, using Altera embedded system development tool kit. The implemented finite field calculation IPs can be used as library modules as Elliptic Curve Cryptography finite field operations which has more than 193 bit key length.

• Journal of Advanced Navigation Technology
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• v.15 no.2
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• pp.298-306
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• 2011

In this paper, the RUNCODE encoder hardware IP was designed and implemented for symbol ID code length encoding, which is one of major modules of JBIG2 encoder for FAX. ImpulseC Codeveloper and Xilinx ISE/EDK program are used for the hardware generation and synthesis of VHDL code. The synthesized hardware was downloaded to Virtex-4 FX60 FPGA on ML410 development board. The synthesized hardware utilizes 13% of total slice of FPGA. Using Active-HDL tool, the hardware was verified showing normal operation. Compared with the software operating using Microblaze cpu on ML410 board, the synthesized hardware was better in operation time. The improvement ratio of operation time between the synthesized hardware and software showed about 40 times faster than software only operation. The synthesized H/W and S/W module cooperated to succeed in compressing the CCITT standard document.