• Proceedings of the KAIS Fall Conference
• /
• 2003.06a
• /
• pp.250-252
• /
• 2003

본 논문에서는 콘벌루션 부호를 사용한 대역확산 방식의 디지틀 통신모뎀을 FPGA를 이용하여 설계 및 검증을 하였다. 대역확산 방식에서의 콘벌루tus부호기(K=3, R=1/2), PN code(128chip) generator와 비터비 디코더를 Xilinx사의 FPGA 디자인 툴인 Xilinx Foundations3.1을 사용하여 VHDL simulation과 timing simulation을 수행하였고, FPGA 회로설계 검증 장비인 EDA-Lab 3000 장비를 사용하여 Xilinx사의 SPARTAN2 2S100PQ208칩에 configuration 한 후 Agilent사의 1681A logic analyzer를 사용하여 설계된 회로의 동작을 검증하였다.

• The KIPS Transactions:PartA
• /
• v.8A no.4
• /
• pp.479-488
• /
• 2001

As the SoC designs complexity constantly increases, the simulation that uses their software models simply takes too much time. To solve this problem, FPGA-based logic emulators have been developed and commonly used in the industry. However, FPGA-based logic emulators are facing with the problems of which not only very low FPGA resource usage rate due to the very limited number of pins in FPGAs, but also the emulation speed getting slow drastically as the complexity of designs increases. In this paper, we proposed a new innovative emulation architecture and its software that has high FPGA resource usage rate and makes the emulation extremely fast. The proposed emulation system has merits to overcome the FPGA pin limitation by pipelined ring which transfers multiple logic signal through a single physical pin, and it also makes possible to use a high speed system clock through the intelligent ring topology. In this topology, not only all signal transfer channels among EPGAs are totally separated from user logic so that a high speed system clock can be used, but also the depth of combinational paths is kept swallow as much as possible. Both of these are contributed to achieve high speed emulation. For pipelined singnals transfer among FPGAs we adopt a few heuristic scheduling having low computation complexity. Experimental result with a 12 bit microcontroller has shown that high speed emulation possible even with these simple heuristic scheduling algorithms.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2020.11a
• /
• pp.182-185
• /
• 2020

특정 통신 프로토콜을 지원하는 물리 계층 트랜시버(PHY)가 없을 때 물리 계층의 부재로 인해 해당 프로토콜이 사용된 통신 시스템을 구현할 수 없다. 그래서 PHY 의 부재는 프로토콜 연구에 큰 걸림돌이 된다. 이런 경우 FPGA 로 물리 계층을 구현할 수 있다. FPGA 를 사용하면 목적과 상황에 맞춰 물리 계층을 구현할 수 있다는 장점이 있다. 통신 속도, 채널의 개수, 오류 검출 알고리즘 등 프로토콜의 다양한 요소를 사용자의 마음대로 구현할 수 있다. 본 논문에는 10Mbps 이더넷 통신에 대한 물리 계층을 FPGA 로 구현하는 실험을 담고 있다. 결과적으로 물리 계층의 구현에 성공했지만 검증에는 실패하였다. 실험에 사용된 보드에는 이더넷 PHY 가 장착되어 있었다. 이더넷 PHY 가 수신 신호를 간섭해서 물리 계층의 동작성을 검증할 수 없었다. 추후에 이더넷 PHY 를 제거하고 재실험을 진행할 것이다. 비록 검증에는 실패했지만, 실험을 통해 FPGA 로 물리 계층을 구현할 수 있음을 보이고 통신 프로토콜 연구 방법으로 이를 제안하고자 한다.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.22 no.5
• /
• pp.105-110
• /
• 2022

Domestically, we are capable of designing high-end memory semiconductors, but not in processors, resulting in unbalance. Using Vivado as a development enivronment and implementing the processor on a Xilinx FPGA reduces time and cost dramatically. In this paper, the popular language VHDL which is widely used in Europe, universities, and research centers around the world for the digital system design is used for designing a pipelined 32-bit ARM processor, implemented on FPGA and verified by Integrated Logic Analyzer. As a result, the ARM processor implemented on FPGA could execute ARM instructions successfully.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.2
• /
• pp.24-30
• /
• 2009

In this paper, the FPGA modem platform complying with 3GPP Release 7 eHSPA specifications and its regularized verification flow are proposed. The FFGA platform consists of modem board supporting physical layer requirements, MCU and DSP core embedded control board to drive the modem board, and peripheral boards for RF interfacing and various equipment interfaces. On the other hand, the proposed verification flow has been regularized into three categories according to the correlation degrees of hardware-software inter-operation, such as simple function test, scenario test call processing and system-level performance test. When it comes to real implementations, the emulation verification strategy for low power mobile SoC is also introduced.

• Proceedings of the KAIS Fall Conference
• /
• 2002.11a
• /
• pp.159-162
• /
• 2002

본 논문에서는 대역확산 방식으로 제안되고 있는 CDMA 시스템의 송수신 모뎀을 FPGA를 이용하여 설계 및 검증을 수행하였다. 송신기에서는 Walsh code(N=16), PN(7 stage=127chip)code를 데이터에 곱하여서 송신하고, 수신기에서는 송신기에서 사용했던 Walsh code(N=16)와 PN code를 사용하여 역확산 후 source data를 확인하였다. 송수신기의 설계는 Xilinx사의 FPGA 디자인 툴인 Xilinx foundation3.1을 사용하여 VHDL simulation을 수행하였고, FPGA 회로설계 검증 장비인 EDA-Lab 3000 장비를 사용하여 Xilinx사의 SPARTAN2 2S100PQ208칩에 다운로드 한 후 에뮬레이션 툴 인 Design-Pro shop을 사용하여 설계된 회로의 동작을 확인하였다.

• Journal of KIISE:Computer Systems and Theory
• /
• v.35 no.5
• /
• pp.231-236
• /
• 2008

This paper proposes a cost-efficient and flexible FPGA-based logic circuit emulation platform. By improving the performance and adding more features, this new platform is an enhanced version of our LAPG. It consists of an FPGA-based hardware engine and software element to drive the emulation and monitor the results. It also provides an interactive verification environment which uses an efficient communication protocol through a bi-directional serial link between the host and the FPGA board. The experimental results show that this new approach saves $55%{\sim}99%$ of communication overhead compared with other methods. According to the test results, the new LAPG is more area efficient in complex circuits with many I/O ports.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.25 no.12
• /
• pp.1914-1919
• /
• 2021

With the development of advanced industries, research on image processing hardware is essential, and timing verification at the gate level is required for actual chip operation. For FPGA-based verification, DDR3 memory interface was previously applied. But recently, as the FPGA specification has improved, DDR4 memory is used. In this case, when a previously used memory interface is applied, the timing mismatch of signals may occur and thus cannot be used. This is due to the difference in performance between CPU and memory. In this paper, the problem is solved through state optimization of the existing interface system FSM. In this process, data read speed is doubled through AXI Data Width modification. For actual case analysis, ZC706 using DDR3 memory and ZCU106 using DDR4 memory among Xilinx's SoC boards are used.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.4
• /
• pp.84-92
• /
• 2002

As today's field programmable gate arrays have very large logic capacity as well as relatively fast operation speed, they're widely used in many application areas. However, debugging the design implemented in FPGA's is very time-consuming and painful as the internal signal probing usually requires large number of FPGA re-compilations, which take tremendously long time. In this paper, we analyze the problems in FPGA debugging and propose a new powerful debugging solution. With the proposed FPGA debugging solution, we can guarantee not only to provide 100% internal signal visibility without FPGA re-compilation for the design in FPGA's, but also to identify at least one design bug per FPGA compilation. An experimental result has clearly shown the proposed approach to FPGA debugging very powerful and practical.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2007.10a
• /
• pp.131-134
• /
• 2007

In this paper, we propose the 1D-CZP pattern for FPGA verification. The algorithm that was implemented by Verilog-HDL on FPGA board is verified before the chip is producted. Input through the external sensor might not be enough to verify the algorithm on FPGA board. Hence, both external input and internal input can lead the verification of the algorithm. This paper suggests the hardware implementation of compact 1D-CZP pattern that has the random input. It is useful to analyze the characteristics of the filter frequencies and organized as ROM Table which is efficient to Modulus operation.