• Title/Summary/Keyword: FPGA

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Implementation of the Digital Current Control System for an Induction Motor Using FPGA (FPGA를 이용한 유도 전동기의 디지털 전류 제어 시스템 구현)

  • Yang, Oh
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.11
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    • pp.21-30
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    • 1998
  • In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.

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REGO: REconfiGurable system emulatOr (레고 : 재구성 가능한 시스템 에뮬레이터)

  • Kim, Nam-Do;Yang, Se-Yang
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.2
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    • pp.91-103
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    • 2002
  • For massive FPGA based emulator, the interconnection architecture and the transmission method of signals between FPGA's are important elements which decide speed of emulation and extendability of emulator. Existing FPGA-based emulation system is faced the problems of which the emulation speed getting slow drastically as the complexity of circuit increases. In this paper, we proposed a new innovative emulation architecture that has high resource usage rate and makes the fast emulation Possible. The emulator with very unique hierarchical ring topology Presented here has merits to overcome FPGA pin limitation by connecting each FPGA into a set of pipelined rings, and it also makes emulation speed at the tens of MHz at least even at system level where the verification complexity can easily exceed the verification capability of designers.

Design of Interface Module for Driving of Image Processing Using FPGA (FPGA를 이용한 영상처리 구동을 위한 정합모듈 설계)

  • Jung, Sung-Hyuck;Kim, Jung-Tae
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.9
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    • pp.2071-2077
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    • 2010
  • Interface modules design between image sensor and external components are designed by FPGA (Field Programmable Gate Array) in this paper. Generally speaking, to satisfy synchronization for the poor quality data in image, SRAM is needed. To receive synchronization signal and image signal data with pixel dimension, the proposed interface logic technique is implemented. From the proposed technique, we can obtain more clear screen by implementing with pixel dimension. Operating frequency of image sensor and that of TFT-LCD are 50MHz and 6.5MHz, respectively. Most of control logic functions are embedded in FPGA. The designed logic gate counter has 33,216 and is designed by Quartus II.

FPGA Design of Turbo Code based on MAP (MAP 기반 터보코드의 FPGA 설계)

  • Seo, Young-Ho
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.3C
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    • pp.306-313
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    • 2007
  • In this paper, we efficiently implemented turbo code algorithm in FPGA H/W(hardware) resource. The used turbo code algorithm has the characteristics; the size of constraint is 3, encoder type is 1/3, the size of random interleaver is 2048. The proposed H/W consists of MAP block for calculating alpha and delta using delta value, storing buffer for each value, multiplier for calculating lamda, and lamda buffer. The proposed algorithm and H/W architecture was verified by C++ language and was designed by VHDL. Finally the designed H/W was programmed into FPGA and tested in wireless communication environment for field availability. The target FPGA of the implemented H/W is VERTEX4 XC4VFX12-12-SF363 and it is stably operated in 131.533MHz clock frequency (7.603ns).

An Implementation of SoC FPGA-based Real-time Object Recognition and Tracking System (SoC FPGA 기반 실시간 객체 인식 및 추적 시스템 구현)

  • Kim, Dong-Jin;Ju, Yeon-Jeong;Park, Young-Seak
    • IEMEK Journal of Embedded Systems and Applications
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    • v.10 no.6
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    • pp.363-372
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    • 2015
  • Recent some SoC FPGA Releases that integrate ARM processor and FPGA fabric show better performance compared to the ASIC SoC used in typical embedded image processing system. In this study, using the above advantages, we implement a SoC FPGA-based Real-Time Object Recognition and Tracking System. In our system, the video input and output, image preprocessing process, and background subtraction processing were implemented in FPGA logics. And the object recognition and tracking processes were implemented in ARM processor-based programs. Our system provides the processing performance of 5.3 fps for the SVGA video input. This is about 79 times faster processing power than software approach based on the Nios II Soft-core processor, and about 4 times faster than approach based the HPS processor. Consequently, if the object recognition and tracking system takes a design structure combined with the FPGA logic and HPS processor-based processes of recent SoC FPGA Releases, then the real-time processing is possible because the processing speed is improved than the system that be handled only by the software approach.

FPGA-DSP Based Implementation of Lane and Vehicle Detection (FPGA와 DSP를 이용한 실시간 차선 및 차량인식 시스템 구현)

  • Kim, Il-Ho;Kim, Gyeong-Hwan
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.12C
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    • pp.727-737
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    • 2011
  • This paper presents an implementation scheme of real-time lane and vehicle detection system with FPGA and DSP. In this type of implementation, defining the functionality of each device in efficient manner is of crucial importance. The FPGA is in charge of extracting features from input image sequences in reduced form, and the features are provided to the DSP so that tracking lanes and vehicles are performed based on them. In addition, a way of seamless interconnection between those devices is presented. The experimental results show that the system is able to process at least 15 frames per second for video image sequences with size of $640{\times}480$.

FPGA Design of Digital Circuit for TACAN (TACAN을 위한 디지털 회로의 FPGA 구현)

  • Seo, Young-Ho;Choi, Hyun-Jun;Kim, Dong-Wook
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.12B
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    • pp.1175-1182
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    • 2010
  • In this paper, we implemented a digital circuit which is targeted on FPGA for estimating azimuth information and distance between aircraft and ground station. All functions for signal processing of TACAN were integrated into a FPGA. The proposed hardware consists of input interface, register file, decoder, signal generator and main controller block. The designed hardware includes a function to generating pulse pair group for azimuth information, a function to responding the interrogation of aircraft for estimating distance between aircraft and ground station, and a function to provide ID information of ground station. The proposed hardware was implemented with FPGA chipset of ALTERA and occupied with 7,071 logic elements.

Implementation of back propagation algorithm for wearable devices using FPGA (FPGA를 이용한 웨어러블 디바이스를 위한 역전파 알고리즘 구현)

  • Choi, Hyun-Sik
    • The Journal of Korean Institute of Next Generation Computing
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    • v.15 no.2
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    • pp.7-16
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    • 2019
  • Neural networks can be implemented in variety of ways, and specialized chips is being developed for hardware improvement. In order to apply such neural networks to wearable devices, the compactness and the low power operation are essential. In this point of view, a suitable implementation method is a digital circuit design using field programmable gate array (FPGA). To implement this system, the learning algorithm which takes up a large part in neural networks must be implemented within FPGA for better performance. In this paper, a back propagation algorithm among various learning algorithms is implemented using FPGA, and this neural network is verified by OR gate operation. In addition, it is confirmed that this neural network can be used to analyze various users' bio signal measurement results by learning algorithm.

Development of High-Speed Real-Time Image Signal Processing Unit for Small Infrared Image Tracking Radar (소형 적외선영상 호밍시스템용 고속 실시간 영상신호처리기 개발)

  • Kim, Hong-Rak;Park, Jin-Ho;Kim, Kyoung-Il;Jeon, Hyo-won;Shin, Jung-Sub
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.21 no.4
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    • pp.43-49
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    • 2021
  • A small infrared image homing system is a tracking system that has an infrared image sensor that identifies a target through the day and night infrared image processing of the target on the ground and searches for and detects the target with respect to the main target. This paper describes the development of a board equipped with a high-speed CPU and FPGA (Field Programmable Gate Array) to identify target through real-time image processing by acquiring target information through infrared image. We propose a CPU-FPGA combining architecture for CPU and FPGA selection and video signal processing, and also describe a controller design using FPGA to control infrared sensor.

Cascade CNN with CPU-FPGA Architecture for Real-time Face Detection (실시간 얼굴 검출을 위한 Cascade CNN의 CPU-FPGA 구조 연구)

  • Nam, Kwang-Min;Jeong, Yong-Jin
    • Journal of IKEEE
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    • v.21 no.4
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    • pp.388-396
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    • 2017
  • Since there are many variables such as various poses, illuminations and occlusions in a face detection problem, a high performance detection system is required. Although CNN is excellent in image classification, CNN operatioin requires high-performance hardware resources. But low cost low power environments are essential for small and mobile systems. So in this paper, the CPU-FPGA integrated system is designed based on 3-stage cascade CNN architecture using small size FPGA. Adaptive Region of Interest (ROI) is applied to reduce the number of CNN operations using face information of the previous frame. We use a Field Programmable Gate Array(FPGA) to accelerate the CNN computations. The accelerator reads multiple featuremap at once on the FPGA and performs a Multiply-Accumulate (MAC) operation in parallel for convolution operation. The system is implemented on Altera Cyclone V FPGA in which ARM Cortex A-9 and on-chip SRAM are embedded. The system runs at 30FPS with HD resolution input images. The CPU-FPGA integrated system showed 8.5 times of the power efficiency compared to systems using CPU only.