• Title/Summary/Keyword: FPGA

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Experimental Verification of Heat Sink for FPGA Thermal Control (FPGA 열제어용 히트싱크 효과의 실험적 검증)

  • Park, Jin-Han;Kim, Hyeon-Soo;Ko, Hyun-Suk;Jin, Bong-Cheol;Seo, Hak-Keum
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.42 no.9
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    • pp.789-794
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    • 2014
  • The FPGA is used to the high speed digital satellite communication on the Digital Signal Process Unit of the next generation GEO communication satellite. The high capacity FPGA has the high power dissipation and it is difficult to satisfy the derating requirement of temperature. This matter is the major factor to degrade the equipment life and reliability. The thermal control at the equipment level has been worked through thermal conduction in the space environment. The FPGA of CCGA or BGA package type was mounted on printed circuit board, but the PCB has low efficient to the thermal control. For the FPGA heat dissipation, the heat sink was applied between part lid and housing of equipment and the performance of heat sink was confirmed via thermal vacuum test under the condition of space qualification level. The FPGA of high power dissipation has been difficult to apply for space application, but FPGA with heat sink could be used to space application with the derating temperature margin.

Design and Implementation of a Multi-level Simulation Environment for WSN: Interoperation between an FPGA-based Sensor Node and a NS3 (FPGA 기반 센서 노드와 NS3 연동을 통한 다층 무선 센서 네트워크 모의 환경 설계 및 구현)

  • Seok, Moon Gi;Kim, Tag Gon;Park, Daejin
    • Journal of the Korea Society for Simulation
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    • v.25 no.4
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    • pp.43-52
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    • 2016
  • Wireless sensor network (WSN) technology has been implemented using commercial off-the-shelf microcontrollers (MCUs), In this paper, we propose a simulation environment to realize the physical evaluation of FPGA-based node by considering vertically cross-layered WSN in terms of physical node device and network interconnection perspective. The proposed simulation framework emulates the physical FPGA-based sensor nodes to interoperate with the NS3 through the runtime infrastructure (RTI). For the emulation and interoperation of FPGA-based nodes, we extend a vendor-providing FPGA design tool from the host computer and a script to execute the interoperation procedures. The standalone NS-3 is also revised to perform interoperation through the RTI. To resolve the different time-advance mechanisms between the FPGA emulation and event-driven NS3 simulation, the pre-simulation technique is applied to the proposed environment. The proposed environment is applied to IEEE 802.15.4-based low-rate, wireless personal area network communication.

Design of FPGA Adaptive Filter for ECG Signal Preprocessing (FPGA를 이용한 심전도 전처리용 적응필터 설계)

  • 한상돈;전대근;이경중;윤형로
    • Journal of Biomedical Engineering Research
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    • v.22 no.3
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    • pp.285-291
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    • 2001
  • In this paper, we designed two preprocessing adaptive filter - high pass filter and notch filter - using FPGA. For minimizing the calculation load of multi-channel and high-resolution ECG system, we utilize FPGA rather than digital signal processing chip. To implement the designed filters in FPGA, we utilize FPGA design tool(Altera corporation, MAX-PLUS II) and CSE database as test data. In order to evaluate the performance in terms of processing time, we compared the designed filters with the digital filters implemented by ADSP21061(Analog Devices). As a result, the filters implemented by FPGA showed better performance than the filters based on ADSP21061. As a consequence of examination, we conclude that FPGA is a useful solution in multi-channel and high-resolution signal processing.

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A Design of a Full FPGA-based DC-motor Control and Monitoring System (Full FPGA 기반 DC 모터 제어 및 모니터링 시스템 설계)

  • Lim, Byung Gyu;Kang, Moon Ho
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.11
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    • pp.211-220
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    • 2014
  • In this paper a full FPGA-based and compact motor-control system is shown that makes it easy to control the motor and analyze the result data in real time with embedding not only a DC motor controller but also a TFT LCD interface in a single FPGA. Both a PID speed control module for a DC motor and a monitoring module for plotting real time graphs on to a TFT LCD are designed in a single FPGA, and the system validity is shown through simulation and experimental results. The FPGA used is xc3s400 and the entire system is designed by using the AD (Altium Designer). A PWM motor drive system is constructed by using MOSFETs for a DC motor 4-quadrant operations.

FPGA-Based Post-Quantum Cryptography Hardware Accelerator Design using High Level Synthesis (HLS 를 이용한 FPGA 기반 양자내성암호 하드웨어 가속기 설계)

  • Haesung Jung;Hanyoung Lee;Hanho Lee
    • Transactions on Semiconductor Engineering
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    • v.1 no.1
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    • pp.1-8
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    • 2023
  • This paper presents the design and implementation of Crystals-Kyber, a next-generation postquantum cryptography, as a hardware accelerator on an FPGA using High-Level Synthesis (HLS). We optimized the Crystals-Kyber algorithm using various directives provided by Vitis HLS, configured the AXI interface, and designed a hardware accelerator that can be implemented on an FPGA. Then, we used Vivado tool to design the IP block and implement it on the ZYNQ ZCU106 FPGA. Finally, the video was recorded and H.264 compressed with Python code in the PYNQ framework, and the video encryption and decryption were accelerated using Crystals-Kyber hardware accelerator implemented on the FPGA.

Design and Implementation of FPGA Based Real-Time Adaptive Beamformer for AESA Radar Applications (능동위상배열 레이더 적용을 위한 FPGA 기반 실시간 적응 빔 형성기 설계 및 구현)

  • Kim, Dong-Hwan;Kim, Eun-Hee;Park, Jong-Heon;Kim, Seon-Joo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.26 no.4
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    • pp.424-434
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    • 2015
  • Adaptive beamforming algorithms have been widely used to remove interference and jamming in the phased array radar system. Advances in the field programmable gate array(FPGA) technology now make possible the real time processing of adaptive beamforming (ABF) algorithm. In this paper, the FPGA based real-time implementation method of adaptive beamforming system(beamformer) in the pre-processor module for active electronically scanned array(AESA) radar is proposed. A compact FPGA-based adaptive beamformer is developed using commercial off the shelf(COTS) FPGA board with communication via OpenVPX(Virtual Path Cross-connect) backplane. This beamformer comprises a number of high speed complex processing including QR decomposition & back substitution for matrix inversion and complex vector/matrix calculations. The implemented result shows that the adaptive beamforming patterns through FPGA correspond with results of simulation through Matlab. And also confirms the possibility of application in AESA radar due to the real time processing of ABF algorithm through FPGA.

Implementation of FPGA Verification System with Slave FIFO Interface and FX3 USB 3 Bridge Chip (FX3 USB 3 브릿지 칩과 slave FIFO 인터페이스를 사용하는 FPGA 검증 시스템 구현)

  • Choi, Byeong-Yoon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.25 no.2
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    • pp.259-266
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    • 2021
  • USB bus not only works with convenience but also transmits data fast and becomes a standard peripheral interface between FPGA development board and personal computer. In this paper FPGA verification system with slave FIFO interface for Cypress FX3 USB 3 bridge chip was implemented. The designed slave FIFO interface consists of host interface module based on FIFO structure, master bus controller and command decoder and supports streaming communication interface for FX3 bridge chip and memory-mapped input and output interface for user design circuit. The ZestSC3 board with Cypress FX3 USB 3 bridge chip and Xilinx Artix FPGA(XC7A35T-1C5G3241) was used to implement FPGA verification system. It was verified that the FPGA verification system for user design circuit operated correctly under various clock frequencies using GUI software developed by visual C# and C++ DLL. The designed slave FIFO interface for FPGA verification system has modular structure and can be applicable to the different user designs with memory-mapped I/O interface.

Soft error correction controller for FPGA configuration memory (FPGA 재구성 메모리의 소프트에러 정정을 위한 제어기의 설계)

  • Baek, Jongchul;Kim, Hyungshin
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.11
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    • pp.5465-5470
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    • 2012
  • FPGA(Field Programmable Gate Array) devices are widely used due to their merits in circuit development time, and development cost. Among various FPGA technologies, SRAM-based FPGAs have large cell capacity so that they are attractive for complex circuit design and their reconfigurability. However, they are weak in space environment where radiation energy particles cause Single Event Upset(SEU). In this paper, we designed a controller supervising SRAM-based FPGA to protect configuration memory inside. The controller is implemented on an Anti-Fusing FPGA. Radiation test was performed on the implemented computer board and the result show that our controller provides better SEU-resilience than TMR-only system.

Availability Analysis of Xilinx 7-Series FPGA against Soft Error (Xilinx 7-Series FPGA의 소프트 에러에 대한 가용성 분석)

  • Ryu, Sang-Moon
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2016.10a
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    • pp.655-658
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    • 2016
  • Xilinx 7-Series FPGA(Field Programmable Gate Array)s mainly used for the implementation of high-performance digital circuit have SRAM-type configuration memory and can malfunction when soft errors occur in their configuration memory. SEM(Soft Error Mitigation Controller) offered by Xilinx helps users mitigate the influence of soft errors in configuration memory. When soft errors occur, SEM Controller can recover the state of FPGA through partial reconfiguration if the soft errors are correctable by ECC(Error Correction Code) and CRC(Cyclic Redundancy Code). This paper presents the availability analysis of Xilinx 7-Series FPGAs against soft errors under the protection of the SEM Controller. Availability functions are derived and compared according to the correction capability of the SEM Controller. The result may help to estimate the reliability of SRAM-based FPGA running in an environment where soft errors may occur.

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Field Programmable Gate Array Reliability Analysis Using the Dynamic Flowgraph Methodology

  • McNelles, Phillip;Lu, Lixuan
    • Nuclear Engineering and Technology
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    • v.48 no.5
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    • pp.1192-1205
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    • 2016
  • Field programmable gate array (FPGA)-based systems are thought to be a practical option to replace certain obsolete instrumentation and control systems in nuclear power plants. An FPGA is a type of integrated circuit, which is programmed after being manufactured. FPGAs have some advantages over other electronic technologies, such as analog circuits, microprocessors, and Programmable Logic Controllers (PLCs), for nuclear instrumentation and control, and safety system applications. However, safety-related issues for FPGA-based systems remain to be verified. Owing to this, modeling FPGA-based systems for safety assessment has now become an important point of research. One potential methodology is the dynamic flowgraph methodology (DFM). It has been used for modeling software/hardware interactions in modern control systems. In this paper, FPGA logic was analyzed using DFM. Four aspects of FPGAs are investigated: the "IEEE 1164 standard," registers (D flip-flops), configurable logic blocks, and an FPGA-based signal compensator. The ModelSim simulations confirmed that DFM was able to accurately model those four FPGA properties, proving that DFM has the potential to be used in the modeling of FPGA-based systems. Furthermore, advantages of DFM over traditional reliability analysis methods and FPGA simulators are presented, along with a discussion of potential issues with using DFM for FPGA-based system modeling.