• Proceedings of the Korea Information Processing Society Conference
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• 2002.04b
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• pp.1285-1288
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• 2002

Bluetooth wireless technology is a publicly available specification proposed for Radio Frequency (RF) communication for short-range and point-to- multipoint voice and data transfer. It operates in the 2.4GHz ISM(Industrial, Scientific and Medical) band and offers the potential for low-cost, broadband wireless access for various mobile and portable devices at range of about 10 meters. In this paper, we describe the structure and the test results of the bluetooth baseband module we have developed. This module was developed based on IP reuse. So Interface of each module such as link controller UART, and audio CODEC is designed based on ARM7 comfortable processor. We also considered various interfaces of related external chips. The fully synthesizable baseband module was fabricated in a $0.25{\mu}m$ CMOS technology occupying $2.79{\times}2.8mm^2$ area including the ARM TDMI processor. And a FPGA implementation of this module is tested for file and bit-stream transfers between PCs.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.11
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• pp.1564-1570
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• 2015

This paper intends to suggest a sensing circuit of PWM voltage for a motor emulator operated in the inverter. In the emulation of the motor using a power converter, it is necessary to measure instantaneous voltage at the PWM voltage loaded from the inverter. Using a filter can generate instantaneous voltage, while it is difficult to follow the rapidly changing inverter voltage caused by the propagation delay and signal attenuation. The method of measuring the duty of PWM using FPGA can generate output voltage from the one-cycle delay of PWM, while the cost of hardware is increasing in order to acquire high precision. This paper suggests a PWM voltage sensing circuit using the analogue system that shows high precision, one-cycle delay of PWM and low-cost hardware. The PWM voltage sensing circuit works in the process of integrating input voltage for valid time by comparing levels of three-phase PWM input voltage, and produce the output value integrated at zero vector. As a result of PSIM simulation and the experiment with the produced hardware, it was verified that the suggested circuit in this paper is valid.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.10
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• pp.1460-1468
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• 2015

As the number of IoT service increases, the interest of lightweight block cipher algorithm, which consists of simple operations with low-power and high speed, is growing. LEA(Leightweight Encryption Algorithm) is recently adopted as one of lightweight encryption standards in Korea. In this paper a pipeline LEA architecture is proposed to process large amounts of data with high throughput. The proposed pipeline LEA can communicate with external modules in the 32-bit I/O interface. It consists of input, output and encryption pipeline stages which take 4 cycles using a muti-cycle pipeline technique. The experimental results showed that the proposed pipeline LEA achieved more than 7.5 Gbps even though the key length was varied. Compared with the previous high speed LEA in accordance with key length of 128, 192, and 256 bits, the throughput of the pipeline LEA was improved 6.45, 7.52, and 8.6 times. Also the throughput per area was improved 2, 1.82, and 2.1 times better than the previous one.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1738-1739
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• 2007

초음파 모터는 고정자와 회전자를 가압마찰하기 위해서 내부에 원형 판 스프링을 이용하고 있다. 출력 토크를 높이기 위해서 이러한 내부 스프링의 강도를 크게 하면 홀딩 토크 역시 커지게 된다. 이로 인하여 기동 시 많은 전류가 소모되며 일반적인 구동 파라미터에 따른 속도 특성 등 기존의 스프링 강도를 지닌 초음파모터(모델명 : 신생공업사(일) USR60-s1)의 특성과는 전혀 다른 특성을 보인다. 본 논문에서는 스프링이 강화된 새로운 타입의 초음파모터(모델명 : 신생공업사(일) USR60-s3)를 가지고 무부하 시의 속도 특성을 실험하였다. 이를 위해 FPGA를 이용해서 디지털 다중 초음파 모터 제어기를 설계하였고, 2상입력 전원의 주파수, 위상차, 주파수-위상차 다중 파라미터 등을 조절하면서 무부하 속도 특성을 측정하였다. 그 결과 홀딩토크가 강화된 초음파 모터의 경우 일반적인 기존 초음파 모터와 비교했을 때 전혀 다른 특성을 보이고, 위상차-주파수 다중 파라미터 조절방식이 조절방식임을 보인다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.9
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• pp.3266-3285
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• 2014

With limited computing and storage resources, many network applications of encryption algorithms require low power devices and fast computing components. CHESS-64 is designed by employing simple key scheduling and Data-Dependent operations (DDO) as main cryptographic components. Hardware performance for Field Programmable Gate Arrays (FPGA) and for Application Specific Integrated Circuits (ASIC) proves that CHESS-64 is a very flexible and powerful new cipher. In this paper, the security of CHESS-64 block cipher under related-key differential cryptanalysis is studied. Based on the differential properties of DDOs, we construct two types of related-key differential characteristics with one-bit difference in the master key. To recover 74 bits key, two key recovery algorithms are proposed based on the two types of related-key differential characteristics, and the corresponding data complexity is about $2^{42.9}$ chosen-plaintexts, computing complexity is about $2^{42.9}$ CHESS-64 encryptions, storage complexity is about $2^{26.6}$ bits of storage resources. To break the cipher, an exhaustive attack is implemented to recover the rest 54 bits key. These works demonstrate an effective and general way to attack DDO-based ciphers.

• Journal of Multimedia Information System
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• v.5 no.2
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• pp.131-138
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• 2018

This work describes a binary image based fast Difference of Gaussian (DoG) filter using zero-dimensional (0-d) convolution and state machine look up tables (LUTs) for image and video stitching hardware platforms. The proposed approach for using binary images to obtain DoG filtering can significantly reduce the data size compared to conventional gray scale based DoG filters, yet binary images still preserve the key features of the image such as contours, edges, and corners. Furthermore, the binary image based DoG filtering can be realized with zero-dimensional convolution and state machine LUTs which eliminates the major portion of the adder and multiplier blocks that are generally used in conventional DoG filter hardware engines. This enables fast computation time along with the data size reduction which can lead to compact and low power image and video stitching hardware blocks. The proposed DoG filter using binary images has been implemented with a FPGA (Altera DE2-115), and the results have been verified.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.2
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• pp.139-144
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• 2011

The modern digital logic technology does not yet satisfy the speed requirements of real-time DSP circuits due to synchronized operation of multiplication and accumulation. This operation degrades DSP performance. Therefore, the double-base number system (DBNS) has emerged in DSP system as an alternative methodology because of fast multiplication and hardware simplicity. In this paper, authors propose a novel multiplication architecture. One operand is an output of a flash analog-to-digital converter (ADC) in DBNS format, while the other operand is a coefficient in the IEEE standard floating-point number format. The DBNS digital output from ADC is produced through a new double base number encoder (DBNE). The multiplied output is in the format of the IEEE standard floating-point number (FPNS). The proposed circuits process multiplication and conversion together. Compared to a typical multiplier that uses the FPNS, the proposed multiplier also consumes 45% less gates, and 44% faster than the FPNS multiplier on Spartan-3 FPGA board. The design is verified with FIR filter applications.

• Journal of Power Electronics
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• v.18 no.6
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• pp.1830-1843
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• 2018

In this paper, the generation of a reference current and voltage signal based on a Kalman filter is offered for a 3-phase 4wire UPQC (Unified Power Quality Conditioner). The performance of the UPQC is improved with source voltages that are distorted due to harmonic components. Despite harmonic and frequency variations, the Kalman filter is capable enough to determine the amplitude and the phase angle of load currents and source voltages. The calculation of the first state is sufficient to identify the fundamental components of the current, voltage and angle. Therefore, the Kalman state estimator is fast and simple. A Kalman based control strategy is proposed and implemented for a UPQC in a distribution system. The performance of the proposed control strategy is assessed for all possible source conditions with varying nonlinear and linear loads. The functioning of the proposed control algorithm with a UPQC is scrutinized and validated through simulations employing MATLAB/Simulink software. Using a FPGA SPATRAN 3A DSP board, the proposed algorithm is developed and implemented. A small-scale laboratory prototype is built to verify the simulation results. The stated control scheme for the UPQC reduces the following issues, voltage sags, voltage swells, harmonic distortions (voltage and current), unbalanced supply voltage and unbalanced power factor under dynamic and steady-state operating conditions.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.2
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• pp.366-373
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• 2007

In this paper we propose a multi-channel speech pickup system for calling quality enhancement of hands-free communication using ALTERA Nios-II processor. Multi-channel speech pickup system uses Delay-and-Sum beamformer with zero-padding interpolator. This paper implements speech pickup system using the Nios-II processor with real-time I/O data processing speed. The proposes speech pickup embedded system shows a good agreement with those of computer simulation(MATLAB) and conventional DSP processor(TMS320C6711) result. The proposed method is effective more than previous methods in cost and design processing time. As a result, LE(Logic Element) of hardware used 3,649/5,980(61%) on a chip.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1458-1466
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• 2019

Multilevel inverters have appeared as a successful and utilitarian solution in many power applications. The prime objective of an inverter is to keep the fundamental component of the output voltage of a multilevel inverter at a preferred value. Equally important is the need to keep the harmonic components in the output voltage within stated harmonic limits. Therefore, the basis of this research is to develop a harmonic minimization function that optimizes the switching angles of cascaded H-bridge multilevel inverter. Due to benefits of the Cuckoo Search (CS) algorithm, it is applied to determine the switching angles, which are further used to generate the switching pattern for firing the H-bridges of multilevel inverter. Simulation results are compared with SPWM based firing scheme. The switching frequency for SPWM firing scheme is taken as 200 Hz since the switching losses are increased when switching frequency is high. To validate the ability of Cuckoo Search optimized firing scheme in minimization of harmonics, experimental results obtained from hardware prototype of Five Level Cascaded H-Bridge Multilevel Inverter equipped with a FPGA controller are presented to verify the simulation results.